公开(公告)号：US06187633B1

公开(公告)日：2001-02-13

申请号：US09169437

申请日：1998-10-09

申请人： Zhong Dong ,  Joe Hui ,  Anqing Zhang

发明人： Zhong Dong ,  Joe Hui ,  Anqing Zhang

IPC分类号： H01L218247

CPC分类号： H01L21/28211 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/511

摘要： The invention is a method of manufacturing a semiconductor memory device using a novel intergate dielectric stack. A key feature of of the invention is the novel O/N/SiON/O structure, forming a silicon oxynitride layer on the silicon nitride layer. The method begins by forming a first insulating layer and a first conductive layer on a semiconductor substrate having one conductivity type. A second insulating layer is formed on the first conducting layer by sequentially stacking: a first silicon oxide layer; a silicon nitride layer; a silicon oxynitride layer; and a second silicon oxide layer. A second conductive layer is formed on the second insulating layer. The first insulating layer, the first conductive layer, the second insulating layer, and the second conductive layer are patterned to form a floating gate, an intergate dielectric, and a control gate. Finally, a source and drain are formed to complete the memory device.

摘要翻译： 本发明是一种制造使用新颖的隔间电介质叠层的半导体存储器件的方法。 本发明的一个关键特征是新型O / N / SiON / O结构，在氮化硅层上形成氧氮化硅层。 该方法开始于在具有一种导电类型的半导体衬底上形成第一绝缘层和第一导电层。 第一绝缘层通过顺序堆叠形成在第一导电层上：第一氧化硅层; 氮化硅层; 氧氮化硅层; 和第二氧化硅层。 在第二绝缘层上形成第二导电层。 将第一绝缘层，第一导电层，第二绝缘层和第二导电层图案化以形成浮栅，隔栅电介质和控制栅极。 最后，形成源极和漏极以完成存储器件。