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公开(公告)号：US20240313115A1
公开(公告)日：2024-09-19
申请号：US18670557
申请日：2024-05-21
发明人： Jia-Chuan YOU , Chia-Hao CHANG , Yu-Ming LIN , Chih-Hao WANG
IPC分类号： H01L29/78 , H01L21/28 , H01L21/321 , H01L21/768 , H01L29/417 , H01L29/49 , H01L29/51 , H01L29/66
CPC分类号： H01L29/7851 , H01L21/28088 , H01L21/3212 , H01L21/76829 , H01L29/41791 , H01L29/4966 , H01L29/66545 , H01L29/6656 , H01L29/6681 , H01L29/511
摘要： A method includes a gate electrode, a first spacer, a second spacer, a metal cap, and a dielectric structure. The gate electrode is over a substrate. The first spacer structure extends along a first sidewall of the gate electrode. The second spacer structure extends along a second sidewall of the gate electrode. The metal cap is over the gate electrode. The dielectric structure is over the gate electrode, the first spacer structure, and the second spacer structure. The dielectric structure has a top segment higher than a top segment of the metal cap.
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公开(公告)号：US20240304719A1
公开(公告)日：2024-09-12
申请号：US18667032
申请日：2024-05-17
发明人： Marie DENISON , Sameer PENDHARKAR , Guru MATHUR
IPC分类号： H01L29/78 , H01L21/225 , H01L21/283 , H01L21/324 , H01L21/8234 , H01L29/06 , H01L29/08 , H01L29/10 , H01L29/40 , H01L29/423 , H01L29/51 , H01L29/66
CPC分类号： H01L29/7813 , H01L21/225 , H01L21/283 , H01L21/324 , H01L21/823487 , H01L29/063 , H01L29/0696 , H01L29/0878 , H01L29/0882 , H01L29/1095 , H01L29/404 , H01L29/407 , H01L29/408 , H01L29/4236 , H01L29/42376 , H01L29/51 , H01L29/511 , H01L29/517 , H01L29/518 , H01L29/66734 , H01L29/7809 , H01L29/42368 , H01L29/4238
摘要： A semiconductor device having a vertical drain extended MOS transistor may be formed by forming deep trench structures to define vertical drift regions of the transistor, so that each vertical drift region is bounded on at least two opposite sides by the deep trench structures. The deep trench structures are spaced so as to form RESURF regions for the drift region. Trench gates are formed in trenches in the substrate over the vertical drift regions. The body regions are located in the substrate over the vertical drift regions.
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公开(公告)号：US12021148B2
公开(公告)日：2024-06-25
申请号：US18295198
申请日：2023-04-03
发明人： Jia-Chuan You , Chia-Hao Chang , Yu-Ming Lin , Chih-Hao Wang
IPC分类号： H01L29/78 , H01L21/28 , H01L21/321 , H01L21/768 , H01L29/417 , H01L29/49 , H01L29/51 , H01L29/66
CPC分类号： H01L29/7851 , H01L21/28088 , H01L21/3212 , H01L21/76829 , H01L29/41791 , H01L29/4966 , H01L29/66545 , H01L29/6656 , H01L29/6681 , H01L29/511
摘要： A method includes a gate structure, gate spacers, a gate helmet, a metal cap, and a gate contact. The gate structure is over a substrate. The gate spacers are on either side of the gate structure. The gate helmet is over the gate structure and the gate spacers. The metal cap is in the gate helmet over the gate structure. The gate contact is over the metal cap. The gate contact forms an interface with the metal cap at a different level height than top segments of the gate spacers.
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公开(公告)号：US11929394B2
公开(公告)日：2024-03-12
申请号：US17575148
申请日：2022-01-13
申请人： ROHM CO., LTD.
发明人： Yuki Nakano , Ryota Nakamura
IPC分类号： H01L29/06 , H01L29/10 , H01L29/16 , H01L29/20 , H01L29/36 , H01L29/40 , H01L29/417 , H01L29/423 , H01L29/49 , H01L29/51 , H01L29/78
CPC分类号： H01L29/063 , H01L29/0619 , H01L29/0657 , H01L29/0661 , H01L29/0692 , H01L29/0696 , H01L29/1602 , H01L29/1608 , H01L29/2003 , H01L29/36 , H01L29/407 , H01L29/41741 , H01L29/4236 , H01L29/4238 , H01L29/4925 , H01L29/511 , H01L29/517 , H01L29/518 , H01L29/7809 , H01L29/7811 , H01L29/7813 , H01L29/7825 , H01L29/0649 , H01L29/1095 , H01L29/41766 , H01L29/42372 , H01L29/42376
摘要： A semiconductor device of the present invention includes a semiconductor layer of a first conductivity type having a cell portion and an outer peripheral portion disposed around the cell portion, formed with a gate trench at a surface side of the cell portion, and a gate electrode buried in the gate trench via a gate insulating film, forming a channel at a portion lateral to the gate trench at ON-time, the outer peripheral portion has a semiconductor surface disposed at a depth position equal to or deeper than a depth of the gate trench, and the semiconductor device further includes a voltage resistant structure having a semiconductor region of a second conductivity type formed in the semiconductor surface of the outer peripheral portion.
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公开(公告)号：US20230343847A1
公开(公告)日：2023-10-26
申请号：US18340758
申请日：2023-06-23
发明人： Chung-Liang CHENG
IPC分类号： H01L29/49 , H01L29/51 , H01L29/423 , H01L29/40 , H01L21/8238 , H01L29/66 , H01L29/786 , H01L27/092 , H01L29/06
CPC分类号： H01L29/4908 , H01L29/511 , H01L29/42392 , H01L29/42364 , H01L29/401 , H01L21/823857 , H01L29/66742 , H01L29/78696 , H01L27/092 , H01L21/823807 , H01L29/0665
摘要： A device comprises a substrate, a semiconductor channel over the substrate, and a gate structure over and laterally surrounding the semiconductor channel. The gate structure comprises a first dielectric layer comprising a first dielectric material including dopants. A second dielectric layer is on the first dielectric layer, and comprises a second dielectric material substantially free of the dopants. A metal fill layer is over the second dielectric layer.
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公开(公告)号：US11777030B2
公开(公告)日：2023-10-03
申请号：US17680864
申请日：2022-02-25
申请人： ROHM CO., LTD.
发明人： Shuhei Mitani , Yuki Nakano , Heiji Watanabe , Takayoshi Shimura , Takuji Hosoi , Takashi Kirino
IPC分类号： H01L29/78 , H01L21/02 , H01L21/04 , H01L21/82 , H01L29/417 , H01L29/423 , H01L29/51 , H01L29/66 , H01L29/10 , H01L29/16 , H01L29/08 , H01L29/45
CPC分类号： H01L29/7827 , H01L21/0223 , H01L21/02164 , H01L21/02178 , H01L21/02236 , H01L21/02247 , H01L21/049 , H01L21/0445 , H01L21/8213 , H01L29/0847 , H01L29/1087 , H01L29/1608 , H01L29/41766 , H01L29/4236 , H01L29/42356 , H01L29/42368 , H01L29/511 , H01L29/513 , H01L29/518 , H01L29/66068 , H01L29/78 , H01L29/7802 , H01L29/7813 , H01L21/02252 , H01L21/02255 , H01L29/086 , H01L29/0869 , H01L29/45
摘要： A semiconductor device includes a semiconductor layer of a first conductivity type. A well region that is a second conductivity type well region is formed on a surface layer portion of the semiconductor layer and has a channel region defined therein. A source region that is a first conductivity type source region is formed on a surface layer portion of the well region. A gate insulating film is formed on the semiconductor layer and has a multilayer structure. A gate electrode is opposed to the channel region of the well region where a channel is formed through the gate insulating film.
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公开(公告)号：US20180350983A1
公开(公告)日：2018-12-06
申请号：US16100804
申请日：2018-08-10
发明人： Won Keun CHUNG , Jong Ho PARK , Seung Ha OH , Sang Yong KIM , Hoon Joo NA , Sang Jin HYUN
IPC分类号： H01L29/78 , H01L29/66 , H01L29/423 , H01L29/51 , H01L21/324 , H01L29/06 , H01L21/283
CPC分类号： H01L29/7831 , B82Y10/00 , H01L21/283 , H01L21/324 , H01L29/0653 , H01L29/0673 , H01L29/0676 , H01L29/42356 , H01L29/42364 , H01L29/42392 , H01L29/4908 , H01L29/511 , H01L29/513 , H01L29/66439 , H01L29/66484 , H01L29/66666 , H01L29/775 , H01L29/7827 , H01L29/78696
摘要： A semiconductor device and a method for fabricating the same are provided. The semiconductor device includes first and second gate stack structures formed in first and second regions, respectively, wherein the first gate stack structure is formed adjacent a first channel region and comprises a first gate insulating film having a first thickness formed on the first channel region, a first function film having a second thickness formed on the first gate insulating film and a first filling film having a third thickness formed on the first function film, wherein the second gate stack structure is formed adjacent a second channel region and comprises a second gate insulating film having the first thickness formed on the second channel region, a second function film having the second thickness formed on the second gate insulating film and a second filling film having the third thickness formed on the second function film, wherein the first and second function films, respectively, comprise TiN and Si concentrations that are different from each other.
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公开(公告)号：US20180308850A1
公开(公告)日：2018-10-25
申请号：US16021959
申请日：2018-06-28
申请人： SK hynix Inc.
发明人： Dong-Kyun KANG , Ho-Jin CHO
IPC分类号： H01L27/108 , H01L29/49 , H01L29/423 , H01L29/51 , H01L29/417
CPC分类号： H01L27/10823 , H01L21/02164 , H01L21/02175 , H01L21/02178 , H01L21/02181 , H01L21/02186 , H01L21/02189 , H01L21/823418 , H01L27/10814 , H01L27/10876 , H01L27/10891 , H01L29/41783 , H01L29/4236 , H01L29/4958 , H01L29/4966 , H01L29/511 , H01L29/513 , H01L29/517 , H01L29/66621 , H01L29/66628
摘要： A semiconductor device includes a substrate comprising a trench; a gate dielectric layer formed over a surface of the trench; a gate electrode positioned at a level lower than a top surface of the substrate, and comprising a lower buried portion embedded in a lower portion of the trench over the gate dielectric layer and an upper buried portion positioned over the lower buried portion; and a dielectric work function adjusting liner positioned between the lower buried portion and the gate dielectric layer; and a dipole formed between the dielectric work function adjusting liner and the gate dielectric layer.
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公开(公告)号：US20180197866A1
公开(公告)日：2018-07-12
申请号：US15914599
申请日：2018-03-07
申请人： SK hynix Inc.
发明人： Dong-Kyun KANG , Ho-Jin CHO
IPC分类号： H01L27/108 , H01L29/423 , H01L29/51 , H01L21/02
CPC分类号： H01L27/10823 , H01L21/02164 , H01L21/02175 , H01L21/02178 , H01L21/02181 , H01L21/02186 , H01L21/02189 , H01L21/823418 , H01L27/10814 , H01L27/10876 , H01L27/10891 , H01L29/41783 , H01L29/4236 , H01L29/4958 , H01L29/4966 , H01L29/511 , H01L29/513 , H01L29/517 , H01L29/66621 , H01L29/66628
摘要： A semiconductor device includes a substrate comprising a trench; a gate dielectric layer formed over a surface of the trench; a gate electrode positioned at a level lower than a top surface of the substrate, and comprising a lower buried portion embedded in a lower portion of the trench over the gate dielectric layer and an upper buried portion positioned over the lower buried portion; and a dielectric work function adjusting liner positioned between the lower buried portion and the gate dielectric layer; and a dipole formed between the dielectric work function adjusting liner and the gate dielectric layer.
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公开(公告)号：US10002939B1
公开(公告)日：2018-06-19
申请号：US15434437
申请日：2017-02-16
发明人： Kangguo Cheng , Ruilong Xie , Tenko Yamashita , Chun-Chen Yeh
IPC分类号： H01L23/48 , H01L29/51 , H01L29/66 , H01L29/06 , H01L29/423 , H01L29/786
CPC分类号： H01L29/511 , B82Y10/00 , H01L29/0649 , H01L29/0673 , H01L29/41725 , H01L29/4238 , H01L29/42392 , H01L29/4908 , H01L29/517 , H01L29/518 , H01L29/66439 , H01L29/66545 , H01L29/66742 , H01L29/66772 , H01L29/66795 , H01L29/775 , H01L29/78654 , H01L29/78696 , H01L2029/42388
摘要： Provided is a method for forming a semiconductor structure. In embodiments, the method includes forming multiple channel nanosheets in multiple first stacks over a substrate. The channel nanosheets in the first stack define first stack cavities such that each pair of adjacent stacked channel nanosheets in the first stack is separated by one of the first stack cavities. The method further includes forming multiple channel nanosheets in a second stack over a substrate. The channel nanosheets in the second stack defining second stack cavities such that each pair of adjacent stacked channel nanosheets in the first second is separated by one of the second stack cavities. The method further includes filling the first stack cavities with a first gate dielectric material and filling the second stack cavities with a work function metal and a second gate dielectric material. The first gate dielectric material differs from the second gate dielectric material.
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