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公开(公告)号：US06927473B2
公开(公告)日：2005-08-09
申请号：US10620054
申请日：2003-07-14
IPC分类号： H01L23/525 , H01L29/00
CPC分类号： H01L21/76888 , H01L23/5256 , H01L23/5258 , H01L2924/0002 , H01L2924/00
摘要： Fuses for integrated circuits and semiconductor devices, methods for making and using the same, and semiconductor devices containing the same. The semiconductor fuse contains two conductive layers, an overlying and underlying layer, on an insulating substrate. The underlying layer comprises titanium nitride and the overlying layer comprises tungsten silicide. The semiconductor fuse may be fabricated during manufacture of a local interconnect structure containing the same materials. The fuse, which may be used to program redundant circuitry, is blown by electrical current rather than laser beams, thus allowing the fuse width to be smaller than prior art fuses blown by laser beams. The fuse may also be blown by less electrical current than the current required to blow conventional polysilicon fuses having similar dimensions.
摘要翻译： 用于集成电路和半导体器件的保险丝，其制造和使用的方法以及包含该保险丝的半导体器件。 半导体熔丝在绝缘基板上包含两层导电层，一层覆盖和下层。 底层包括氮化钛，上覆层包括硅化钨。 半导体保险丝可以在制造包含相同材料的局部互连结构时制造。 可用于编程冗余电路的保险丝由电流而不是激光束吹扫，从而允许熔丝宽度小于由激光束吹制的现有技术的熔丝。 熔断器也可能被吹过比吹出具有相似尺寸的常规多晶硅保险丝所需的电流更小的电流。
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公开(公告)号：US07109105B2
公开(公告)日：2006-09-19
申请号：US10838587
申请日：2004-05-04
IPC分类号： H01L21/8234 , H01L21/44
CPC分类号： H01L21/76888 , H01L23/5256 , H01L23/5258 , H01L2924/0002 , H01L2924/00
摘要： Fuses for integrated circuits and semiconductor devices and methods for using the same. The semiconductor fuse contains two conductive layers, an overlying and underlying refractory metal nitride layer, on an insulating substrate. The semiconductor fuse may be fabricated during manufacture of a local interconnect structure including the same materials. The fuse, which may be used to program redundant circuitry, may be blown by electrical current rather than laser beams, thus allowing the fuse width to be smaller than prior art fuses blown by laser beams. The fuse may also be blown by less electrical current than the current required to blow conventional polysilicon fuses having similar dimensions.
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公开(公告)号：US06511868B2
公开(公告)日：2003-01-28
申请号：US09901761
申请日：2001-07-09
IPC分类号： H01L2182
CPC分类号： H01L21/76888 , H01L23/5256 , H01L23/5258 , H01L2924/0002 , H01L2924/00
摘要： Fuses for integrated circuits and semiconductor devices, methods for making the same, methods of using the same, and semiconductor devices containing the same. The semiconductor fuse contains two conductive layers-an overlying and underlying layer-on an insulating substrate. The underlying layer comprises titanium nitride and the overlying layer comprises tungsten silicide. The semiconductor fuse may be fabricated during manufacture of a local interconnect structure containing the same materials. The fuse, which may be used to program redundant circuitry, is blown by electrical current rather than laser beams, thus allowing the fuse width to be smaller than prior art fuses blown by laser beams. The fuse may also be blown by less electrical current than the current required to blow conventional polysilicon fuses having similar dimensions.
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4.发明授权Semiconductor fuses, methods of using the same, methods of making the same, and semiconductor devices containing the same 有权半导体熔丝，其使用方法，制造方法以及包含该半导体熔丝的半导体器件公开(公告)号：US06277674B1
公开(公告)日：2001-08-21
申请号：US09165754
申请日：1998-10-02
IPC分类号： H01L2182
CPC分类号： H01L21/76888 , H01L23/5256 , H01L23/5258 , H01L2924/0002 , H01L2924/00
摘要： Fuses for integrated circuits and semiconductor devices, methods for making the same, methods of using the same, and semiconductor devices containing the same. The semiconductor fuse contains two conductive layers—an overlying and underlying layer—on an insulating substrate. The underlying layer comprises titanium nitride and the overlying layer comprises tungsten silicide. The semiconductor fuse may be fabricated during manufacture of a local interconnect structure containing the same materials. The fuse, which may be used to program redundant circuitry, is blown by electrical current rather than laser beams, thus allowing the fuse width to be smaller than prior art fuses blown by laser beams. The fuse may also be blown by less electrical current than the current required to blow conventional polysilicon fuses having similar dimensions.
摘要翻译： 用于集成电路和半导体器件的保险丝，其制造方法，使用该保险丝的方法以及包含该保险丝的半导体器件。 半导体熔丝在绝缘基板上包含两层导电层 - 覆盖层和下层。 底层包括氮化钛，上覆层包括硅化钨。 半导体保险丝可以在制造包含相同材料的局部互连结构时制造。 可用于编程冗余电路的保险丝由电流而不是激光束吹扫，从而允许熔丝宽度小于由激光束吹制的现有技术的熔丝。 熔断器也可能被吹过比吹出具有相似尺寸的常规多晶硅保险丝所需的电流更小的电流。
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公开(公告)号：US07816246B2
公开(公告)日：2010-10-19
申请号：US11499134
申请日：2006-08-03
IPC分类号： H01L21/8234 , H01L21/44
CPC分类号： H01L21/76888 , H01L23/5256 , H01L23/5258 , H01L2924/0002 , H01L2924/00
摘要： Fuses for integrated circuits and semiconductor devices and methods for using the same. The semiconductor fuse contains two conductive layers, an overlying and underlying refractory metal nitride layer, on an insulating substrate. The semiconductor fuse may be fabricated during manufacture of a local interconnect structure including the same materials. The fuse, which may be used to program redundant circuitry, may be blown by electrical current rather than laser beams, thus allowing the fuse width to be smaller than prior art fuses blown by laser beams. The fuse may also be blown by less electrical current than the current required to blow conventional polysilicon fuses having similar dimensions.
摘要翻译： 用于集成电路和半导体器件的保险丝及其使用方法。 半导体熔丝在绝缘基板上包含两层导电层，一层覆盖和下层的难熔金属氮化物层。 可以在制造包括相同材料的局部互连结构的过程中制造半导体熔丝。 可以用于编程冗余电路的保险丝可以由电流而不是激光束吹扫，从而允许熔丝宽度小于由激光束熔断的现有技术的熔丝。 熔断器也可能被吹过比吹出具有相似尺寸的常规多晶硅保险丝所需的电流更小的电流。
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6.发明授权Semiconductor fuses, methods of using the same, methods of making the same, and semiconductor devices containing the same 有权半导体熔丝，其使用方法，制造方法以及包含该半导体熔丝的半导体器件公开(公告)号：US06703263B2
公开(公告)日：2004-03-09
申请号：US10331033
申请日：2002-12-27
IPC分类号： H01L2182
CPC分类号： H01L21/76888 , H01L23/5256 , H01L23/5258 , H01L2924/0002 , H01L2924/00
摘要： Fuses for integrated circuits and semiconductor devices, methods for making the same, methods of using the same, and semiconductor devices containing the same. The semiconductor fuse contains two conductive layers—an overlying and underlying layer—on an insulating substrate. The underlying layer comprises titanium nitride and the overlying layer comprises tungsten silicide. The semiconductor fuse may be fabricated during manufacture of a local interconnect structure containing the same materials. The fuse, which may be used to program redundant circuitry, is blown by electrical current rather than laser beams, thus allowing the fuse width to be smaller than prior art fuses blown by laser beams. The fuse may also be blown by less electrical current than the current required to blow conventional polysilicon fuses having similar dimensions.
摘要翻译： 用于集成电路和半导体器件的保险丝，其制造方法，使用该保险丝的方法以及包含该保险丝的半导体器件。 半导体熔丝在绝缘基板上包含两层导电层 - 覆盖层和下层。 底层包括氮化钛，上覆层包括硅化钨。 半导体保险丝可以在制造包含相同材料的局部互连结构时制造。 可用于编程冗余电路的保险丝由电流而不是激光束吹扫，从而允许熔丝宽度小于由激光束吹制的现有技术的熔丝。 熔断器也可能被吹过比吹出具有相似尺寸的常规多晶硅保险丝所需的电流更小的电流。
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公开(公告)号：US06583473B1
公开(公告)日：2003-06-24
申请号：US09584005
申请日：2000-05-30
IPC分类号： H01L2701
CPC分类号： H01L21/761 , H01L21/8238 , H01L27/0928
摘要： An intermediate semiconductor device for use in making surface channel MOS transistors is disclosed. The intermediate semiconductor device includes a semiconductor substrate having a top surface, a bottom surface, a plurality of doped isolation regions and a first surface channel. A first dielectric layer overlies a first portion of the top surface of the semiconductor substrate and a portion of at least one of the plurality of doped isolation regions. A first polysilicon layer overlies the first dielectric layer, and a second dielectric layer overlies the first polysilicon layer and a second portion of the top surface of the semiconductor substrate. The second dielectric layer is overlaid with a second polysilicon layer.
摘要翻译： 公开了一种用于制造表面沟道MOS晶体管的中间半导体器件。 中间半导体器件包括具有顶表面，底表面，多个掺杂隔离区和第一表面沟道的半导体衬底。 第一电介质层覆盖半导体衬底的顶表面的第一部分和多个掺杂隔离区中的至少一个的一部分。 第一多晶硅层覆盖在第一介电层上，第二介电层覆盖第一多晶硅层和半导体衬底顶表面的第二部分。 第二介质层与第二多晶硅层重叠。
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8.发明授权Surface channel MOS transistors, methods for making the same, and semiconductor devices containing the same 有权表面沟道MOS晶体管，其制造方法以及包含该晶体管的半导体器件
公开(公告)号：US6110788A
公开(公告)日：2000-08-29
申请号：US153931
申请日：1998-09-16
IPC分类号： H01L21/761 , H01L21/8238 , H01L27/092 , H01L21/336
CPC分类号： H01L21/761 , H01L21/8238 , H01L27/0928
摘要： Methods for making surface channel MOS transistors. The methods are practiced by providing a substrate with at least one isolation region, forming a first dielectric layer over the substrate, forming a first polysilicon layer over the first dielectric layer, removing a portion of the first polysilicon layer to expose a portion of the first dielectric layer, forming at least one diffusion region in the substrate underlying the exposed portion of the first dielectric layer, removing the exposed portion of the first dielectric layer, forming a second dielectric layer over the first polysilicon layer and the at least one diffusion region, forming a second polysilicon layer over the second dielectric layer, removing the portion of the second dielectric layer and second polysilicon layer overlying the first polysilicon layer, depositing a conductive layer over the first and second polysilicon layers, depositing a third dielectric layer over the conductive layers and removing a portion of the third dielectric layer, conductive layer, first and second polysilicon layers, and first and second dielectric layers. The conductive layer may be tungsten silicide. These methods provide surface channel MOS transistors using fewer masking steps; flat polysilicon typography which allows fabrication of smaller device features; and tungsten silicide strapped gates scalable to less than 0.25 micrometers with a low resist level.
摘要翻译： 制造表面沟道MOS晶体管的方法。 所述方法通过提供具有至少一个隔离区的衬底来实现，在衬底上形成第一介电层，在第一介电层上形成第一多晶硅层，去除第一多晶硅层的一部分以暴露第一 电介质层，在第一电介质层的暴露部分下方的衬底中形成至少一个扩散区，去除第一电介质层的暴露部分，在第一多晶硅层和至少一个扩散区上形成第二电介质层， 在所述第二介电层上形成第二多晶硅层，去除所述第二介电层的所述部分和覆盖所述第一多晶硅层的第二多晶硅层，在所述第一和第二多晶硅层上沉积导电层，在所述导电层上沉积第三介电层 以及第一和第二绝缘体的第三介电层，导电层的一部分 第二多晶硅层以及第一和第二介电层。 导电层可以是硅化钨。 这些方法提供了使用较少掩模步骤的表面沟道MOS晶体管; 平坦的多晶硅印刷术，允许制造较小的器件特征; 并且钨硅化物带状栅可扩展到小于0.25微米，抗蚀剂水平低。
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公开(公告)号：US20060270208A1
公开(公告)日：2006-11-30
申请号：US11499134
申请日：2006-08-03
申请人： Zhongze Wang , Michael Violette , Jigish Trivedi
发明人： Zhongze Wang , Michael Violette , Jigish Trivedi
CPC分类号： H01L21/76888 , H01L23/5256 , H01L23/5258 , H01L2924/0002 , H01L2924/00
摘要： Fuses for integrated circuits and semiconductor devices and methods for using the same. The semiconductor fuse contains two conductive layers, an overlying and underlying refractory metal nitride layer, on an insulating substrate. The semiconductor fuse may be fabricated during manufacture of a local interconnect structure including the same materials. The fuse, which may be used to program redundant circuitry, may be blown by electrical current rather than laser beams, thus allowing the fuse width to be smaller than prior art fuses blown by laser beams. The fuse may also be blown by less electrical current than the current required to blow conventional polysilicon fuses having similar dimensions.
摘要翻译： 用于集成电路和半导体器件的保险丝及其使用方法。 半导体熔丝在绝缘基板上包含两层导电层，一层覆盖和下层的难熔金属氮化物层。 可以在制造包括相同材料的局部互连结构的过程中制造半导体熔丝。 可以用于编程冗余电路的保险丝可以由电流而不是激光束吹扫，从而允许熔丝宽度小于由激光束熔断的现有技术的熔丝。 熔断器也可能被吹过比吹出具有相似尺寸的常规多晶硅保险丝所需的电流更小的电流。
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公开(公告)号：US20050266666A1
公开(公告)日：2005-12-01
申请号：US11191512
申请日：2005-07-28
申请人： Jigish Trivedi , Zhongze Wang , Chih-Chen Cho , Mike Violette , Todd Abbott
发明人： Jigish Trivedi , Zhongze Wang , Chih-Chen Cho , Mike Violette , Todd Abbott
IPC分类号： G11C11/412 , H01L21/8238 , H01L21/8244 , H01L27/11
CPC分类号： G11C11/412 , H01L21/823842 , H01L21/823871 , H01L21/823878 , H01L27/11 , H01L27/1104
摘要： According to the present invention, an ultrathin buried diffusion barrier layer (UBDBL) is formed over all or part of the doped polysilicon layer of a polysilicide structure composed of the polycrystalline silicon film and an overlying film of a metal, metal silicide, or metal nitride. More specifically, according to one embodiment of the present invention, a memory cell is provided comprising a semiconductor substrate, a P well, an N well, an N type active region, a P type active region, an isolation region, a polysilicide gate electrode structure, and a diffusion barrier layer. The P well is formed in the semiconductor substrate. The N well is formed in the semiconductor substrate adjacent to the P well. The N type active region is defined in the P well and the P type active region is defined in the N well. The isolation region is arranged to isolate the N type active region from the P type active region. The polysilicide gate electrode structure is composed of a polycrystalline silicon film and an overlying metal, metal silicide, or metal nitride film. The polycrystalline silicon film comprises an N+ polysilicon layer formed with the N type active region and a P+ polysilicon layer formed with the P type active region. The diffusion barrier layer is formed in the polysilicide gate electrode structure over a substantial portion of the polycrystalline silicon film between the polycrystalline silicon film and the metal, metal silicide, or metal nitride film.
摘要翻译： 根据本发明，在由多晶硅膜和金属，金属硅化物或金属氮化物的覆盖膜构成的多晶硅结构的全部或部分掺杂多晶硅层上形成超薄掩埋扩散阻挡层（UBDBL） 。 更具体地，根据本发明的一个实施例，提供了一种存储单元，其包括半导体衬底，P阱，N阱，N型有源区，P型有源区，隔离区，多晶硅栅电极 结构和扩散阻挡层。 P阱形成在半导体衬底中。 N阱形成在与P阱相邻的半导体衬底中。 N型有源区定义在P阱中，P型有源区定义在N阱中。 隔离区被配置为将N型有源区与P型有源区隔离。 多晶硅栅电极结构由多晶硅膜和上覆金属，金属硅化物或金属氮化物膜构成。 多晶硅膜包括由N型有源区形成的N +多晶硅层和由P型有源区形成的P +多晶硅层。 多晶硅膜与金属，金属硅化物或金属氮化物膜之间的多晶硅膜的大部分上的多硅化物栅电极结构中形成扩散阻挡层。
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