公开(公告)号：US10671025B2

公开(公告)日：2020-06-02

申请号：US16470410

申请日：2017-12-08

Applicant: ams AG

Inventor： Christian Mautner ,  Friedrich Bahnmueller ,  Friedrich Laengauer ,  Robert Kappel

IPC: H03M1/50 ,  G04F10/00 ,  H03K23/00 ,  H03L7/099 ,  H03M1/12 ,  H03L7/089 ,  H03L7/081 ,  H03M1/10

Abstract: A time-to-digital converter arrangement has a ring oscillator with a plurality of inverting elements and a first and a second counter coupled to the ring oscillator. The first counter is configured to increment a first counter value if a positive edge transition is present at one of the inverting elements. The second counter is configured to increment a second counter value if a negative edge transition is present at the one of the inverting elements. A storage element stores the first and the second counter value and logical states of the plurality of inverting elements. A decoder coupled to the storage element selects one of the first and the second counter value as a valid value based on an evaluation of the stored logical states, and outputs a total counter value based on the valid value and the stored logical states.

公开(公告)号：US20200110368A1

公开(公告)日：2020-04-09

申请号：US16470410

申请日：2017-12-08

Applicant: ams AG

Inventor： Christian Mautner ,  Friedrich Bahnmueller ,  Friedrich Laengauer ,  Robert Kappel

IPC: G04F10/00 ,  H03K23/00

Abstract: A time-to-digital converter arrangement has a ring oscillator with a plurality of inverting elements and a first and a second counter coupled to the ring oscillator. The first counter is configured to increment a first counter value if a positive edge transition is present at one of the inverting elements. The second counter is configured to increment a second counter value if a negative edge transition is present at the one of the inverting elements. A storage element stores the first and the second counter value and logical states of the plurality of inverting elements. A decoder coupled to the storage element selects one of the first and the second counter value as a valid value based on an evaluation of the stored logical states, and outputs a total counter value based on the valid value and the stored logical states.