公开(公告)号：US20160018464A1

公开(公告)日：2016-01-21

申请号：US14804500

申请日：2015-07-21

Applicant: dSPACE digital signal processing and control engineering GmbH

Inventor： Matthias BOCKELKAMP ,  Marc DRESSLER

IPC: G01R31/3177

CPC classification number: G01R31/3177 ,  G06F11/3648 ,  G06F11/3652 ,  G06F11/3656 ,  G06F21/575

Abstract: An arrangement for the partial release of a debug interface of a programmable hardware component, whereby a first logic for the programmable hardware component can be stored in a configuration memory and a configuration device is designed to program the programmable hardware component via a configuration interface of the programmable hardware component according to the first logic. The configuration device is further designed to register a programming process of the programmable hardware component which occurs via the debug interface according to a second logic and, upon termination of the programming process occurring via the debug interface, reprograms the programmable hardware component according to the first logic.

Abstract translation: 用于部分释放可编程硬件组件的调试接口的装置，由此用于可编程硬件组件的第一逻辑可以存储在配置存储器中，并且配置设备被设计为经由可编程硬件组件的配置接口对可编程硬件组件进行编程 可编程硬件组件根据第一逻辑。 所述配置装置还被设计为根据第二逻辑注册经由调试接口发生的可编程硬件组件的编程过程，并且在通过调试接口发生的编程处理结束时，根据第一逻辑重新编程可编程硬件组件 逻辑。

公开(公告)号：US20190251212A1

公开(公告)日：2019-08-15

申请号：US16274951

申请日：2019-02-13

Applicant: dSPACE digital signal processing and control engineering GmbH

Inventor： Marc DRESSLER ,  Matthias BOCKELKAMP

IPC: G06F17/50

CPC classification number: G06F17/505 ,  G06F17/5054

Abstract: A method is disclosed for creating a netlist for the configuration of an FPGA, wherein the code of a first program comprises a multiplicity of subroutines. The code of the first program can be combined with the code of a second program to form a third program. A netlist for the configuration of an FPGA can be created from the third program, wherein at least one first subroutine of the first program is not used at the runtime of the third program. The first subroutine can be recognized in an automated manner, and a fourth program can be created on the basis of the first program. Also, the first subroutine can be removed during the creation of the fourth program, such that the fourth program does not contain the first subroutine.

公开(公告)号：US20160018465A1

公开(公告)日：2016-01-21

申请号：US14804692

申请日：2015-07-21

Applicant: dSPACE digital signal processing and control engineering GmbH

Inventor： Matthias BOCKELKAMP ,  Marc DRESSLER

IPC: G01R31/3177

CPC classification number: G01R31/3177 ,  G06F11/3648 ,  G06F11/3652 ,  G06F11/3656 ,  G06F21/575

Abstract: An arrangement for disabling a configuration of a first programmable hardware component, having the first programmable hardware component, a second programmable hardware component, and a switching element. The first programmable hardware component has a configuration interface for configuring a logic of the first programmable hardware component, a data interface for communication of the logic with the second programmable hardware component, a debugging interface for debugging and configuring the logic, and a configuration monitoring interface for signaling a configuration process of the logic. The switching element is designed and connected to the debugging interface such that access to the debugging interface during a configuration process of the logic can be disabled.

Abstract translation: 一种用于禁用具有第一可编程硬件组件的第一可编程硬件组件，第二可编程硬件组件和开关元件的配置的装置。 第一可编程硬件组件具有用于配置第一可编程硬件组件的逻辑的配置接口，用于与第二可编程硬件组件通信逻辑的数据接口，用于调试和配置逻辑的调试接口以及配置监视接口 用于发信号通知逻辑的配置过程。 开关元件设计并连接到调试接口，使得在逻辑的配置过程中可以禁用对调试接口的访问。