Abstract:
An adapter for connecting an embedded system to a control computer having a standard interface, in particular a network interface, a first subcircuit, and a second subcircuit, the first subcircuit being designed to communicate with the control computer via the standard interface by means of a standard protocol, preferably XCP. The first subcircuit is designed to convert a protocol functionality requested in the standard protocol via the standard interface, out of a set of supported protocol functionalities into the call for one or more elementary functions out of a defined overall set of elementary functions. The first subcircuit is connected to the second subcircuit via an internal interface, wherein the second subcircuit has a programmable computing module which is configured to provide at least one elementary function out of the overall set of elementary functions which can be called up via the internal interface by means of a call.
Abstract:
A method for manipulating a first function of a control program of an electronic control device, using a second function. The control program is processed using a first calculation kernel of a processor, and the second function is processed by a second calculation kernel during the processing of the control program. The first function assigns a first value to a variable and writes the first value to the storage address of the variable at a first time. The second function assigns a second value to the variable, which value is written to the storage address of the variable at a second time, wherein the second value written by the first function is overwritten. At a third time, the control program reads the second value from the storage address of the variable. A control entity coordinates the times at which the storage address of the variable is accessed.
Abstract:
A method is disclosed for creating a netlist for the configuration of an FPGA, wherein the code of a first program comprises a multiplicity of subroutines. The code of the first program can be combined with the code of a second program to form a third program. A netlist for the configuration of an FPGA can be created from the third program, wherein at least one first subroutine of the first program is not used at the runtime of the third program. The first subroutine can be recognized in an automated manner, and a fourth program can be created on the basis of the first program. Also, the first subroutine can be removed during the creation of the fourth program, such that the fourth program does not contain the first subroutine.
Abstract:
An arrangement for disabling a configuration of a first programmable hardware component, having the first programmable hardware component, a second programmable hardware component, and a switching element. The first programmable hardware component has a configuration interface for configuring a logic of the first programmable hardware component, a data interface for communication of the logic with the second programmable hardware component, a debugging interface for debugging and configuring the logic, and a configuration monitoring interface for signaling a configuration process of the logic. The switching element is designed and connected to the debugging interface such that access to the debugging interface during a configuration process of the logic can be disabled.
Abstract:
A method for changing software in a memory of an electronic control unit, wherein each memory address from the overlay memory can be assigned to a memory address in the read-only memory by an assignment information item. During a run time of the control unit, at least a functional part of a bypass routine that is to at least partially replace an original program routine is stored in an address range in the overlay memory, or a jump instruction is stored in the overlay memory as the first part of a bypass routine that refers to a second part of the bypass routine that is stored in an address range accessible to the processor. To activate an overlay functionality the address and/or the address range of the overlay memory are assigned to an address or address range of the program routine to be replaced.
Abstract:
An arrangement for the partial release of a debug interface of a programmable hardware component, whereby a first logic for the programmable hardware component can be stored in a configuration memory and a configuration device is designed to program the programmable hardware component via a configuration interface of the programmable hardware component according to the first logic. The configuration device is further designed to register a programming process of the programmable hardware component which occurs via the debug interface according to a second logic and, upon termination of the programming process occurring via the debug interface, reprograms the programmable hardware component according to the first logic.
Abstract:
A method for changing a software in the memory of an electronic control unit. A bypass routine is stored in the working memory of the electronic control unit, and the address of the bypass function is stored in a table. A service function reads the address from the table and calls the bypass routine. The bypass routine is replaceable at the run time of the electronic control unit by erasing the table entry. The call of the service function is integrated into the program code of the electronic control unit by an overlay memory, a memory management unit, or with the aid of watch points.