公开(公告)号：US11894840B2

公开(公告)日：2024-02-06

申请号：US17711845

申请日：2022-04-01

申请人： pSemi Corporation

发明人： Robert Mark Englekirk ,  Keith Rampmeier ,  Arpita Moghe Chadha

IPC分类号： H03K17/693 ,  H03K19/17736 ,  H03K19/0944 ,  G06F13/42 ,  G06F13/40

CPC分类号： H03K17/693 ,  H03K19/0944 ,  H03K19/17744 ,  G06F13/4068 ,  G06F13/4282

摘要： Circuits and methods for determining the characteristics of swappable pins in a peripheral in a 1-Wire or similar single-conductor system, thereby allowing each one of two pins to be either an I/O pin (connected to an I/O line) or a CAP pin (connected to a storage capacitor). Embodiments may utilize a hybrid buffer circuit that utilizes an effectively bi-directional PFET pull-up device coupled between the swappable pins A and B. Two open-drain NFETs pull-down devices are used, one on either side of the PFET and coupled to a respective pin (A or B), but with only one NFET being selected to be operable based on pin-determination flag signals from the pin detection circuitry. Such a hybrid buffer circuit would consume significantly less IC area than two complete conventional buffers, resulting in less leakage and less yield loss.

公开(公告)号：US20230318598A1

公开(公告)日：2023-10-05

申请号：US17711845

申请日：2022-04-01

申请人： pSemi Corporation

发明人： Robert Mark Englekirk ,  Keith Rampmeier ,  Arpita Moghe Chadha

IPC分类号： H03K17/693 ,  H03K19/17736 ,  H03K19/0944

CPC分类号： H03K17/693 ,  G06F13/4068 ,  H03K19/0944 ,  H03K19/17744

摘要： Circuits and methods for determining the characteristics of swappable pins in a peripheral in a 1-Wire or similar single-conductor system, thereby allowing each one of two pins to be either an I/O pin (connected to an I/O line) or a CAP pin (connected to a storage capacitor). Embodiments may utilize a hybrid buffer circuit that utilizes an effectively bi-directional PFET pull-up device coupled between the swappable pins A and B. Two open-drain NFETs pull-down devices are used, one on either side of the PFET and coupled to a respective pin (A or B), but with only one NFET being selected to be operable based on pin-determination flag signals from the pin detection circuitry. Such a hybrid buffer circuit would consume significantly less IC area than two complete conventional buffers, resulting in less leakage and less yield loss.