公开(公告)号：US20200259499A1

公开(公告)日：2020-08-13

申请号：US16273318

申请日：2019-02-12

Applicant: BAE SYSTEMS Information and Electronic Systems Integration Inc.

Inventor： Randall M. White

IPC: H03M1/06 ,  H03M1/68 ,  H03M1/78

Abstract: Circuit techniques are disclosed for improving the SFDR of a DAC. In an embodiment, a DAC includes a resistor ladder network operably coupled to input logic circuitry and an output. The input logic circuitry receives a multi-bit input signal and effectively creates a plurality of processed input signals therefrom. The resistor ladder network is configured to receive the plurality of processed input signals and includes a corresponding plurality of current paths. Each current path includes: a current switch operably controlled by one of the processed input signals; a first resistor in series with the current switch; a second resistor in series with the first resistor; and a feedforward capacitor in parallel with the second resistor. The output is operably coupled to each of the plurality of current paths and is configured to output an analog output signal that corresponds to the multi-bit input signal.

公开(公告)号：US20200076772A1

公开(公告)日：2020-03-05

申请号：US16114654

申请日：2018-08-28

Applicant: BAE SYSTEMS INFORMATION AND ELECTRONIC SYSTEMS INTEGRATION INC.

Inventor： Benjamin Kapp ,  Jibu Abraham

IPC: H04L29/06 ,  H04L9/08

Abstract: A zero knowledge communications protocol is provided that can unconditionally secure communications sent through a communications network by encrypting all messages, continuously sending noise messages through the network, and routing all network activity through an anonymity network. This combination of components prevent an eavesdropper on the network from garnering any information about when a communication is sent, the contents and statistics of a communication, the sender, or the intended recipient of the communication.

公开(公告)号：US20160308536A1

公开(公告)日：2016-10-20

申请号：US15099753

申请日：2016-04-15

Applicant: BAE Systems Information and Electronic Systems Integration Inc.

Inventor： JOSEPH D. CALI ,  CURTIS M. GRENS ,  LAWRENCE J. KUSHNER ,  STEVEN E. TURNER

IPC: H03K21/02 ,  H03K21/38 ,  H03L7/197

CPC classification number: H03K21/026 ,  G06F1/08 ,  G06F7/68 ,  H03K21/00 ,  H03K21/10 ,  H03K21/38 ,  H03K21/40 ,  H03K23/00 ,  H03K23/40 ,  H03K23/58 ,  H03K23/64 ,  H03K23/68 ,  H03L7/1974

Abstract: Frequency divider techniques are disclosed which can be used to address two problems: when an incorrect division occurs if the modulus control changes before the divide cycle is complete, and when an incorrect division occurs due to a boundary crossing (e.g., power-of-2 boundary crossing in a fractional-N PLL application). In one embodiment, a frequency divider is provided comprising a plurality of flip-flops operatively coupled to carry out division of an input frequency, and configured to generate a modulus output and receive a divided clock signal of a previous cell. An additional flip-flop is selectively clocked off one of the modulus output or the divided clock of the previous stage, depending at least in part on a Skip control signal applied to a data input of the additional flip-flop, and is further configured to selectively reset the plurality of flip-flops to a state that will result in a correct divide ratio.

Abstract translation: 可以使用分频器技术来解决两个问题：如果模数控制在分频周期完成之前变化，并且当由于边界穿越而发生不正确的划分时（例如，功率2 在分数N PLL应用中的边界交叉）。 在一个实施例中，提供了一种分频器，其包括可操作地耦合以执行输入频率划分的多个触发器，并且被配置为产生模数输出并接收先前小区的分频时钟信号。 至少部分地基于施加到附加触发器的数据输入端的跳过控制信号，另外的触发器选择性地将时钟从先前级的模数输出或分频时钟中的一个计时，并进一步被配置为 有选择地将多个触发器复位到将导致正确分频比的状态。