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公开(公告)号：US09634671B2
公开(公告)日：2017-04-25
申请号：US14734316
申请日：2015-06-09
发明人： Martin Cochet , Sylvain Clerc
摘要： A pulse signal generator has an input receiving an initial pulse signal having an initial period, an oscillator generating an oscillator signal, a first stage and a second stage. The first stage is synchronized with the oscillator signal and configured to deliver a secondary pulse signal having a separation between successive pulses that is representative of an integer part of a division of the initial period by an integer N. The first stage further delivers an auxiliary signal representative of a fractional part of the division and containing, for each pulse of the secondary pulse signal, an indication of a time shift to be applied to the pulse taking into account the separation. The second stage is configured to receive the successive pulses and the corresponding time shift indications and generate successive corresponding pulses of an output pulse signal.
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公开(公告)号：US20160079984A1
公开(公告)日：2016-03-17
申请号：US14734316
申请日：2015-06-09
发明人： Martin Cochet , Sylvain Clerc
IPC分类号： H03K21/38
摘要： A pulse signal generator has an input receiving an initial pulse signal having an initial period, an oscillator generating an oscillator signal, a first stage and a second stage. The first stage is synchronized with the oscillator signal and configured to deliver a secondary pulse signal having a separation between successive pulses that is representative of an integer part of a division of the initial period by an integer N. The first stage further delivers an auxiliary signal representative of a fractional part of the division and containing, for each pulse of the secondary pulse signal, an indication of a time shift to be applied to the pulse taking into account the separation. The second stage is configured to receive the successive pulses and the corresponding time shift indications and generate successive corresponding pulses of an output pulse signal.
摘要翻译： 脉冲信号发生器具有接收具有初始周期的初始脉冲信号的输入，产生振荡器信号的振荡器，第一级和第二级。 第一级与振荡器信号同步，并被配置为传送具有表示初始周期的除法的整数部分整数N的连续脉冲之间的间隔的次级脉冲信号。第一级还传送辅助信号 代表除法的分数部分，并且对于次级脉冲信号的每个脉冲包含考虑到分离而应用于脉冲的时间偏移的指示。 第二级被配置为接收连续脉冲和对应的时移指示，并产生输出脉冲信号的连续对应的脉冲。
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公开(公告)号：US09543963B2
公开(公告)日：2017-01-10
申请号：US14609526
申请日：2015-01-30
CPC分类号： H03K23/005 , H03K21/38 , H03K23/40 , H03K23/58 , H03K23/588 , H03K23/64 , H03K23/667
摘要： An input value, where the input value is an amount which the current value of the counter is to be increased is received. The current value of the modulo binary counter and an offset value of the modulo binary counter are increased by the input value. Whether the current value of the counter is greater than or equal to the modulus value of the binary counter is determined. The current value of the counter is replaced with an updated offset value of the counter, where the updated offset value is the offset value of the counter increased by the input value. The updated offset value of the counter is returned.
摘要翻译： 接收输入值是计数器的当前值要增加的量的输入值。 模二进制计数器的当前值和模二进制计数器的偏移值增加输入值。 确定计数器的当前值是否大于或等于二进制计数器的模数值。 计数器的当前值由计数器的更新的偏移值替换，其中更新的偏移值是计数器的偏移值增加输入值。 返回计数器的更新的偏移值。
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公开(公告)号：US20160308536A1
公开(公告)日：2016-10-20
申请号：US15099753
申请日：2016-04-15
CPC分类号： H03K21/026 , G06F1/08 , G06F7/68 , H03K21/00 , H03K21/10 , H03K21/38 , H03K21/40 , H03K23/00 , H03K23/40 , H03K23/58 , H03K23/64 , H03K23/68 , H03L7/1974
摘要： Frequency divider techniques are disclosed which can be used to address two problems: when an incorrect division occurs if the modulus control changes before the divide cycle is complete, and when an incorrect division occurs due to a boundary crossing (e.g., power-of-2 boundary crossing in a fractional-N PLL application). In one embodiment, a frequency divider is provided comprising a plurality of flip-flops operatively coupled to carry out division of an input frequency, and configured to generate a modulus output and receive a divided clock signal of a previous cell. An additional flip-flop is selectively clocked off one of the modulus output or the divided clock of the previous stage, depending at least in part on a Skip control signal applied to a data input of the additional flip-flop, and is further configured to selectively reset the plurality of flip-flops to a state that will result in a correct divide ratio.
摘要翻译： 可以使用分频器技术来解决两个问题：如果模数控制在分频周期完成之前变化，并且当由于边界穿越而发生不正确的划分时（例如，功率2 在分数N PLL应用中的边界交叉）。 在一个实施例中，提供了一种分频器，其包括可操作地耦合以执行输入频率划分的多个触发器，并且被配置为产生模数输出并接收先前小区的分频时钟信号。 至少部分地基于施加到附加触发器的数据输入端的跳过控制信号，另外的触发器选择性地将时钟从先前级的模数输出或分频时钟中的一个计时，并进一步被配置为 有选择地将多个触发器复位到将导致正确分频比的状态。
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5.发明授权公开(公告)号：US07103132B1
公开(公告)日：2006-09-05
申请号：US09531677
申请日：2000-03-20
申请人： Hiroshi Baba
发明人： Hiroshi Baba
CPC分类号： H03L7/193 , H03D13/00 , H03D2200/0084 , H03K23/64 , H03L7/199
摘要： A power saving operation control method and device for a phase comparator unit are provided. The control device includes: a reference signal frequency dividing unit which divides the frequency of a reference signal to generate a reference frequency divided signal; a comparison signal frequency unit which divides an input signal to generate a comparison frequency divided signal; a phase comparator which compares the phases of the reference frequency divided signal and the comparison frequency divided signal; a canceling signal generator which generates a power saving state canceling signal in accordance with the reference frequency divided signal and the comparison frequency divided signal; a first initializing signal generator which generates a first initializing signal for initializing the reference signal frequency dividing unit in accordance with the power saving state canceling signal; and a second initializing signal generator which generates a second initializing signal for initializing the comparison signal frequency dividing unit in accordance with the power saving state canceling signal.
摘要翻译： 提供了一种用于相位比较器单元的省电操作控制方法和装置。 控制装置包括：参考信号分频单元，其分频参考信号的频率以产生参考频率分频信号; 比较信号频率单元，其分割输入信号以生成比较分频信号; 比较基准频率分频信号和比较频率分频信号的相位的相位比较器; 消除信号发生器，其根据所述参考频率分频信号和所述比较分频信号产生省电状态消除信号; 第一初始化信号发生器，其根据省电状态消除信号产生用于初始化参考信号分频单元的第一初始化信号; 以及第二初始化信号发生器，其根据省电状态消除信号产生用于初始化比较信号分频单元的第二初始化信号。
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公开(公告)号：US20190036533A1
公开(公告)日：2019-01-31
申请号：US16071978
申请日：2016-03-16
发明人： Yuki YANAGIHARA , Koji TSUTSUMI
IPC分类号： H03K21/08
CPC分类号： H03K21/08 , H03K23/64 , H03K23/667 , H03L7/18 , H03L7/193
摘要： A setting data output circuit (3) is configured to update setting data in synchronization with a frequency divided signal output from a dual modulus frequency divider on a last stage out of the dual modulus frequency dividers to which a non-significant reset signal is output from a reset circuit (6) which are included in a plurality of dual modulus frequency dividers (1-1 and 1-2) in a first frequency divider group (1). As a result, when a frequency dividing ratio of the dual modulus frequency divider on the last stage out of valid dual modulus frequency dividers contributing to frequency dividing operation is 3, it is possible to realize normal frequency dividing operation even in a case in which frequency dividing ratio setting data to decrease the number of valid dual modulus frequency dividers contributing to the frequency dividing operation is provided.
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公开(公告)号：US09900012B2
公开(公告)日：2018-02-20
申请号：US15099753
申请日：2016-04-15
IPC分类号： H03K21/00 , H03K23/00 , H03K21/02 , H03K21/38 , H03L7/197 , G06F7/68 , H03K23/40 , G06F1/08 , H03K23/64 , H03K21/40 , H03K23/58 , H03K23/68 , H03K21/10
CPC分类号： H03K21/026 , G06F1/08 , G06F7/68 , H03K21/00 , H03K21/10 , H03K21/38 , H03K21/40 , H03K23/00 , H03K23/40 , H03K23/58 , H03K23/64 , H03K23/68 , H03L7/1974
摘要： Frequency divider techniques are disclosed which can be used to address two problems: when an incorrect division occurs if the modulus control changes before the divide cycle is complete, and when an incorrect division occurs due to a boundary crossing (e.g., power-of-2 boundary crossing in a fractional-N PLL application). In one embodiment, a frequency divider is provided comprising a plurality of flip-flops operatively coupled to carry out division of an input frequency, and configured to generate a modulus output and receive a divided clock signal of a previous cell. An additional flip-flop is selectively clocked off one of the modulus output or the divided clock of the previous stage, depending at least in part on a Skip control signal applied to a data input of the additional flip-flop, and is further configured to selectively reset the plurality of flip-flops to a state that will result in a correct divide ratio.
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公开(公告)号：US20160226494A1
公开(公告)日：2016-08-04
申请号：US14609526
申请日：2015-01-30
IPC分类号： H03K23/00
CPC分类号： H03K23/005 , H03K21/38 , H03K23/40 , H03K23/58 , H03K23/588 , H03K23/64 , H03K23/667
摘要： An input value, where the input value is an amount which the current value of the counter is to be increased is received. The current value of the modulo binary counter and an offset value of the modulo binary counter are increased by the input value. Whether the current value of the counter is greater than or equal to the modulus value of the binary counter is determined. The current value of the counter is replaced with an updated offset value of the counter, where the updated offset value is the offset value of the counter increased by the input value. The updated offset value of the counter is returned.
摘要翻译： 接收输入值是计数器的当前值要增加的量的输入值。 模二进制计数器的当前值和模二进制计数器的偏移值增加输入值。 确定计数器的当前值是否大于或等于二进制计数器的模数值。 计数器的当前值由计数器的更新的偏移值替换，其中更新的偏移值是计数器的偏移值增加输入值。 返回计数器的更新的偏移值。
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公开(公告)号：US20050258879A1
公开(公告)日：2005-11-24
申请号：US11060477
申请日：2005-02-18
申请人： Masazumi Marutani
发明人： Masazumi Marutani
摘要： A clock frequency divider is provided which has first through Pth (where P is an integer) sub-counters, each capable of counting M+1 clock pulses and provided in parallel, and first through Pth clock signals are provided to the sub-counters, which has same period as a reference clock signal and are sequentially shifted by 1/P of the period of the reference clock signal. Of the first through Pth sub-counters, when the Nth sub-counter (where N is an arbitrary number from 1 to P) finishes counting a prescribed number M of reference clock pulses, all the other sub-counters are initialized, or, at least the (N+1)th sub-counter is initialized.
摘要翻译： 提供了具有第一到第P（其中P是整数）子计数器的时钟分频器，每个子计数器能够对M + 1个时钟脉冲进行并行并行并行提供，并且第一到第P个时钟信号被提供给子计数器， 其与参考时钟信号具有相同的周期，并且被顺序地移动参考时钟信号的周期的1 / P。 在第一到第P子计数器中，当第N个子计数器（其中N是从1到P的任意数字）完成计数指定数量M的参考时钟脉冲时，所有其他子计数器被初始化，或者在 至少第（N + 1）个子计数器被初始化。
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公开(公告)号：US09762228B2
公开(公告)日：2017-09-12
申请号：US14855238
申请日：2015-09-15
发明人： Neha Agrawal , Sajin Mohamad , Chulkyu Lee
IPC分类号： H03K21/00 , H03K7/06 , H03K19/21 , H03K3/037 , H03K21/10 , H03K23/64 , H03K23/00 , H03K21/02 , G06F1/08
CPC分类号： H03K7/06 , G06F1/08 , H03K3/037 , H03K19/21 , H03K21/00 , H03K21/026 , H03K21/10 , H03K23/00 , H03K23/64
摘要： Systems and methods for dividing input clock signals by programmable divide ratios can produce output clock signals with the delay from the input clock signal to the output clock signal independent of the value of the divide ratio and with the duty cycle of the output clock signal being 50% independent of the value of the divide ratio. An example programmable clock divider includes a modulo N counter that produces a count signal that counts modulo the divide ratio and a half-rate clock signal generator that produces a common half-rate clock signal, an even half-rate clock signal, and an odd half-rate clock signal that toggle at one-half the rate of the output clock signal. The common half-rate clock signal, the even half-rate clock signal, and the odd half-rate clock signal are combined to produce the output clock signal.
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