公开(公告)号：US09591188B2

公开(公告)日：2017-03-07

申请号：US14446374

申请日：2014-07-30

Applicant: Brass Roots Technologies, LLC

Inventor： Bradley William Walker

IPC: G06F3/14 ,  H04N5/04 ,  H04N5/21 ,  G09G3/00 ,  G09G3/20 ,  G09G3/34

CPC classification number: H04N5/04 ,  G06F3/1423 ,  G09G3/002 ,  G09G3/2029 ,  G09G3/3426 ,  G09G2320/0646 ,  H04N5/21

Abstract: The present disclosure pertains to a method for designing cascaded bit sequences for cascaded digital displays. The method avoids unwanted interactions between cascaded sequences in cascaded digital displays. By using sequences with a particular structure, cascaded sequences can be designed such that no sequence is affected by the others. The following rules must be followed in constructing the sequence. First, the display devices must be frame-locked, so that the timing relationship between the sequences is maintained throughout each frame. Second, for each display device, the ratio of bit plane weights must remain constant, regardless of the pixel data displayed on the other display device(s). Third, the amount of bit plane skew must remain constant, regardless of the pixel data displayed on the other display device(s). Fourth, bit plane phased leakage must be compensated for or avoided.

Abstract translation: 本公开涉及用于级联数字显示器的级联比特序列的设计方法。 该方法避免了级联数字显示器中级联序列之间的不必要的相互作用。 通过使用具有特定结构的序列，可以设计级联序列，使得序列不受其他序列的影响。 在构建序列时必须遵循以下规则。 首先，显示设备必须被帧锁定，使得在每个帧中维持序列之间的时序关系。 第二，对于每个显示设备，位平面权重的比率必须保持恒定，而与其他显示设备上显示的像素数据无关。 第三，与其他显示设备上显示的像素数据无关，位平面偏移的量必须保持不变。 第四，位平面分相泄漏必须补偿或避免。