公开(公告)号：US07849441B2

公开(公告)日：2010-12-07

申请号：US11426882

申请日：2006-06-27

申请人： Shridhar Mukund ,  Anjan Mitra ,  Jed Krohnfeldt ,  Clement Leung

发明人： Shridhar Mukund ,  Anjan Mitra ,  Jed Krohnfeldt ,  Clement Leung

IPC分类号： G06F9/44

CPC分类号： G06F17/505 ,  G06F15/7821 ,  G06F15/7867 ,  G06F17/504 ,  G06F17/5045 ,  G06F17/5068 ,  Y02D10/12 ,  Y02D10/13

摘要： A method for specifying stateful, transaction-oriented systems is provided. The method initiates with designating a plurality of primitive FlowModules. The method includes defining at least one FlowGate within each of the plurality of FlowModules, wherein each FlowGate includes a non-interruptible sequence of procedure code, a single point of entry and is invoked by a named concurrent call. An Arc is designated from a calling FlowGate to a called FlowGate and a Signal is generated for each named invocation of the called FlowGate. A Channel is defined for carrying the Signal. Methods for synthesizing a semiconductor device and routing signals in the semiconductor device are provided.

摘要翻译： 提供了一种用于指定有状态的，面向事务的系统的方法。 该方法通过指定多个原始FlowModules来启动。 该方法包括在多个FlowModules中的每一个中定义至少一个FlowGate，其中每个FlowGate包括不可中断的过程代码序列，单个入口点，并由命名的并发调用进行调用。 从调用FlowGate指定一个Arc到被称为FlowGate的Arc，并且为被调用的FlowGate的每个命名调用生成一个Signal。 定义一个通道用于携带信号。 提供了用于在半导体器件中合成半导体器件和路由信号的方法。

公开(公告)号：US07614020B2

公开(公告)日：2009-11-03

申请号：US11426880

申请日：2006-06-27

申请人： Shridhar Mukund ,  Anjan Mitra

发明人： Shridhar Mukund ,  Anjan Mitra

IPC分类号： G06F17/50

CPC分类号： G06F17/505 ,  G06F15/7821 ,  G06F15/7867 ,  G06F17/504 ,  G06F17/5045 ,  G06F17/5068 ,  Y02D10/12 ,  Y02D10/13

摘要： A semiconductor memory device is provided. The semiconductor memory device includes a plurality of memory cells arranged in multiple column groups, each column group having, a plurality of columns and a plurality of external bit-lines for independent multi-way configurable access. The column group having a first, second, and third level of hierarchy in the external bit-lines. The first level of the hierarchy provides connectivity to the plurality of memory cells. The second level of the hierarchy provides a first splicer for multiplexing data to and from each of the columns in the column group to an intermediate bit-line. The third level of the hierarchy includes a second splicer for multiplexing data to and from multiple external access paths to the intermediate bit-line. A structurally reconfigurable circuit device and methods for designing a circuit are also provided.

摘要翻译： 提供半导体存储器件。 半导体存储器件包括布置在多个列组中的多个存储器单元，每个列组具有用于独立多路可配置存取的多个列和多个外部位线。 列组在外部位线中具有第一，第二和第三层级。 层级的第一级提供与多个存储器单元的连接。 层级的第二级提供了用于将数据从列组中的每个列复用到中间位线的第一拼接器。 该层级的第三级包括用于将数据复用到从多个外部访问路径到中间位线的数据的第二拼接器。 还提供了一种结构可重构电路装置和用于设计电路的方法。

公开(公告)号：US20100098266A1

公开(公告)日：2010-04-22

申请号：US12573827

申请日：2009-10-05

申请人： Shridhar Mukund ,  Suresh Agarwal ,  Vivek Nigam

发明人： Shridhar Mukund ,  Suresh Agarwal ,  Vivek Nigam

IPC分类号： H04B15/00

CPC分类号： G10L21/0208 ,  G10L21/0272

摘要： An audio signal enhancement device is provided. The device includes a first and a second microphone, placed as close together as possible, the first and second microphone having receiving surfaces facing in opposing directions. The first and second microphones receive a desired target audio signal originating in the proximity of the microphones and undesired noise signals not originating in the proximity of the microphones. The acoustic pressure gradient from the desired target signal between the first and the second microphones is greater than that from the noise signals. Signal processing logic is provided. The signal processing logic is configured to firstly generate a proximity-indicator signal and a pre-target-estimate signal through a combination of output from the first microphone and output of the second microphone. The signal processing logic is further configured to generate a noise-estimate signal by combining the output from the first microphone with the proximity-indicator and the pre-target-estimate. The signal processing logic is further configured to generate a target-estimate signal by combining the output from the first microphone with the proximity-indicator and the noise-estimate. The signal processing logic is further configured to provide a target signal substantially free from noise by combining the target-estimate, noise-estimate and the proximity-indicator. The embodiments also provide for a noise to signal ratio estimator that provides an indication to a user of the strength of the noise in the signal for a particular location.

摘要翻译： 提供一种音频信号增强装置。 该装置包括第一麦克风和第二麦克风，其尽可能靠近放置，第一和第二麦克风具有面向相反方向的接收表面。 第一和第二麦克风接收始发于麦克风附近的期望的目标音频信号和不是源于麦克风附近的不期望的噪声信号。 来自第一麦克风和第二麦克风之间的期望目标信号的声压梯度大于来自噪声信号的声压级梯度。 提供信号处理逻辑。 信号处理逻辑被配置为首先通过来自第一麦克风的输出和第二麦克风的输出的组合产生接近指示符信号和预定目标估计信号。 所述信号处理逻辑还被配置为通过将来自所述第一麦克风的输出与所述接近指示符和所述预先目标估计相结合来产生噪声估计信号。 信号处理逻辑还被配置为通过组合来自第一麦克风的输出与接近指示符和噪声估计来产生目标估计信号。 信号处理逻辑还被配置为通过组合目标估计，噪声估计和接近度指标来提供基本上没有噪声的目标信号。 实施例还提供了一种噪声信号比估计器，其向用户提供针对特定位置的信号中的噪声强度的指示。

公开(公告)号：US07676783B2

公开(公告)日：2010-03-09

申请号：US11426887

申请日：2006-06-27

申请人： Shridhar Mukund ,  Anjan Mitra

发明人： Shridhar Mukund ,  Anjan Mitra

IPC分类号： G06F17/50

CPC分类号： G06F17/505 ,  G06F15/7821 ,  G06F15/7867 ,  G06F17/504 ,  G06F17/5045 ,  G06F17/5068 ,  Y02D10/12 ,  Y02D10/13

摘要： An apparatus for performing in-memory computation for stateful, transaction-oriented applications is provided. The apparatus includes a multi-level array of storage cells. The storage cells are configurable for a read access from one of a plurality of access data paths. The plurality of access data paths are also configurable for a write access from one of the plurality of access data paths. The multi-level array is capable of being configurable into logical partitions with arbitrary starting addresses. The apparatus further includes a compute element in communication with the multi-level array over the plurality of access data paths, the compute element configured to issue a plurality of memory accesses to the multi-level array through the plurality of access data paths. Methods for programming a multi-level array of storage cells and for processor design are also provided.

摘要翻译： 提供了一种用于对有状态的面向事务的应用执行内存中计算的设备。 该装置包括存储单元的多级阵列。 存储单元可配置用于从多个访问数据路径之一进行读访问。 多个访问数据路径也可配置用于从多个访问数据路径中的一个访问数据路径进行写访问。 多级阵列能够被配置成具有任意起始地址的逻辑分区。 所述设备还包括与所述多个访问数据路径上的所述多级阵列通信的计算元件，所述计算元件被配置为通过所述多个访问数据路径发布对所述多级阵列的多个存储器访问。 还提供了用于编程存储单元的多级阵列和处理器设计的方法。