公开(公告)号：US5323325A

公开(公告)日：1994-06-21

申请号：US663946

申请日：1991-03-18

申请人： Shunzo Izumiya

发明人： Shunzo Izumiya

IPC分类号： B23Q17/00 ,  B23Q41/06 ,  G05B19/4063 ,  G06F11/32 ,  G06F11/34 ,  G06F15/46

CPC分类号： B23Q41/06 ,  G05B19/4063 ,  G06F11/3476 ,  G05B2219/35289 ,  G05B2219/35291 ,  G05B2219/35366 ,  G06F11/32

摘要： A method of displaying an operation history of a machine, which permits quick and proper investigation of the causes of troubles and trouble-shooting therefor. A processor of a numerical control device mounted on the machine writes a block number in a corresponding address region of a memory every time one block of a machining program is read out, and executes the block after an index indicating the address region to be stored with the next block number is determined (S1 to S4, S6). If the determined index exceeds a value indicating the last address region, the index is reset to a value indicating the first address region (S5). During the execution of each block, the processor successively determines, with respect to all the circuit sections of an input/output circuit, the presence/absence of signal transfer through each circuit section (S12), and causes a memory address region corresponding to the block to successively store codes individually indicating those circuit sections concerned in the signal transfer (S13), so that block numbers indicating up-to-date blocks and codes indicating the circuit sections concerned in the signal transfer during the execution of the blocks are continually held in their associated memory address regions, whereby the operation history of the machine is recorded. In response to a display command, the block numbers and codes constituting the operation history are successively displayed on a display screen according to precedence (S21 to S26).

摘要翻译： PCT No.PCT / JP90 / 00931 Sec。 371日期1991年3月18日 102（e）1991年3月18日PCT PCT 1990年7月19日PCT公布。 公开号WO91 / 01197 日期：1991年2月7日。一种显示机器操作历史的方法，可以快速，适当地调查故障原因和故障排除。 安装在机器上的数字控制装置的处理器每当读出加工程序的一个块时，将块号写入存储器的相应地址区域中，并且在指示要存储的地址区域的索引之后执行块 确定下一个块号（S1〜S4，S6）。 如果确定的索引超过表示最后地址区域的值，则将索引重置为指示第一地址区域的值（S5）。 在每个块的执行期间，处理器相对于输入/输出电路的所有电路部分依次确定是否存在通过每个电路部分的信号传送（S12），并且产生对应于 块连续地存储代表信号传送中涉及的那些电路部分的代码（S13），以便连续地保持指示在块执行期间在信号传送中涉及的电路部分的最新块和代码的代码块 在其相关联的存储器地址区域中，由此记录机器的操作历史。 响应于显示命令，构成操作历史的块号和代码根据优先顺序显示在显示屏上（S21至S26）。

公开(公告)号：US5583410A

公开(公告)日：1996-12-10

申请号：US326980

申请日：1994-10-21

申请人： Gary S. Jacobson ,  Wesley A. Kirschner ,  Michael J. Ramadei

发明人： Gary S. Jacobson ,  Wesley A. Kirschner ,  Michael J. Ramadei

IPC分类号： G05B19/40

CPC分类号： G05B19/40 ,  G05B2219/34045 ,  G05B2219/34196 ,  G05B2219/34219 ,  G05B2219/34236 ,  G05B2219/35366 ,  G05B2219/35368 ,  G05B2219/35375 ,  G05B2219/42171 ,  G05B2219/42198

摘要： A plurality of step time tables consisting of a sequence of step times defining intervals between steps and thus a velocity profile to be executed by a stepper motor are stored in a first memory. A step table defining a plurality of identical sequences of excitation pattern for driving a stepper motor is stored in a second table. Identical DMA channels output the step times to a timer and the plurality of exitation patterns to a buffer. The timer measures the duration of the step times and when each step time expires generates a trigger signal which initiates the transfer of the next step time and next excitation pattern through the respective DMA channels. The buffer includes a control register which selects one excitation pattern from the plurality of excitation patterns output from the step table to be output for control of a selected one of a plurality of motors connected to the buffer. The buffer outputs are inverted to form bipolar signals to drive current drivers in accordance with the excitation pattern. The apparatus is initialized by a data processor to select one of the plurality of excitation tables and to select one of the groups of outputs of the buffer to drive a corresponding selected motor. The DMA channel for outputting the step time table is initialized for non-repetitive operation and the DMA channel outputting the step table is initialized for cyclic operation. The direction in which the selected stepper motor is to be driven is determined by the direction in which the step table is accessed.

摘要翻译： 由步进时间序列组成的多个步进时间表被存储在第一存储器中，所述步骤时间序列确定步骤之间的间隔，从而由步进电动机执行的速度分布。 定义用于驱动步进电机的多个相同的激励模式序列的步骤表被存储在第二表中。 相同的DMA通道将步进时间输出到定时器，并将多个退出模式输出到缓冲器。 定时器测量步进时间的持续时间，并且当每个步骤时间到期时，产生触发信号，该触发信号通过相应的DMA通道启动下一个步进时间和下一个激励模式的传送。 该缓冲器包括一个控制寄存器，该控制寄存器从输出步进表的多个激励模式中选择一个激励模式，以输出以控制连接到缓冲器的多个电动机中选定的一个。 缓冲器输出被反相以形成双极信号，以根据激励模式驱动电流驱动器。 所述装置由数据处理器初始化以选择所述多个激励表中的一个，并且选择所述缓冲器的输出组之一以驱动对应的所选择的电动机。 用于输出步进时间表的DMA通道被初始化用于非重复操作，并且输出步骤表的DMA通道被初始化用于循环操作。 所选择的步进电动机的驱动方向由步进台的访问方向决定。

公开(公告)号：US3774165A

公开(公告)日：1973-11-20

申请号：US3774165D

申请日：1972-08-02

申请人： US NAVY

发明人： MCCANN P ,  FISHER W

IPC分类号： G05B19/408 ,  G06F5/16 ,  G06F11/00 ,  G11B5/00

CPC分类号： G06F5/16 ,  G05B19/408 ,  G05B2219/35366 ,  G06F11/076

摘要： An apparatus for processing the flow of digital data encoded upon a tape, but not the information in the digital data, comprising a plurality of digital circuits, and adapted to be connected at its input end to a tape deck containing the tape and at its output end to output interfacing equipment, such as a servo, comprising a clock source for generating the clocking pulses used to control the timing and sequencing of the operations of the digital circuits, which timing may be different from the rate at which the digital data were encoded upon the tape, and an input buffer, connectable to the tape deck, which receives the digital data from the tape in the tape deck. The apparatus further comprises a tape control, connectable to the tape deck, and whose control inputs are derived from the tape deck, which controls the sequencing of the write-in and read-out of the digital data, and a memory which comprises a memory storage, a memory control, and a memory address. The memory is in the form of a double buffer in that digital data may be simultaneously written into one portion, or buffer, of the memory storage and read out of the other buffer. The apparatus further comprises, an output register for accepting the digital data from the memory, and an output control which generates, as an output signal, a strobe pulse to the memory address, which causes reading out of data from the memory storage and distributing this data into its proper place in the output register. A line driver and receiver whose inputs are (1) digital data from the output register, and (2) an ''''output acknowledge'''' signal from the output control, which causes delivery of the digital data to the output interfacing equipment and the outputs of the line driver and receiver, also forms part of the apparatus.

摘要翻译： 一种用于处理在磁带上编码的数字数据流的装置，而不是数字数据中的信息，包括多个数字电路，并且适于在其输入端连接到包含磁带的磁带机和其输出端 结束到诸如伺服的输出接口设备，包括用于产生用于控制数字电路的操作的定时和排序的时钟脉冲的时钟源，该定时可以与数字数据被编码的速率不同 在磁带上，以及可连接到磁带机的输入缓冲器，其从磁带机架中的磁带接收数字数据。 该装置还包括可连接到磁带卡座的磁带控制器，并且其控制输入来自控制数字数据的写入和读出的顺序的磁带机，以及包括存储器的存储器 存储器，存储器控制和存储器地址。 存储器是双缓冲器的形式，其中数字数据可以被同时写入存储器存储器的一部分或缓冲器，并从另一个缓冲器中读出。 该装置还包括：用于从存储器接收数字数据的输出寄存器，以及输出控制，该输出控制器产生作为输出信号的选通脉冲到存储器地址，这导致从存储器存储器中读出数据并将其分配 数据进入输出寄存器的正确位置。 线路驱动器和接收器，其输入是（1）来自输出寄存器的数字数据，以及（2）来自输出控制的“输出确认”信号，其导致将数字数据传送到输出接口设备和输出接口设备的输出 线路驱动器和接收器，也构成设备的一部分。

公开(公告)号：US20030050725A1

公开(公告)日：2003-03-13

申请号：US10241811

申请日：2002-09-11

申请人： SIEMENS AKTIENGESELLSCHAFT

发明人： Rainer Dirnfeldner

IPC分类号： G06F019/00

CPC分类号： G05B19/408 ,  G05B2219/34192 ,  G05B2219/34411 ,  G05B2219/35366

摘要： Process data are recorded by accumulating process data in a delay-time critical cyclic time planenulle.g., a main processor clocknulland storing the accumulated data in an data buffer memory having a FIFO characteristic using a cyclic clock. The data buffer memory is read out in a delay-time uncritical acyclic time planenulle.g., a pre-process clocknulland the read out data are processed and stored as data sets in a log memory. To achieve synchronous recording of process data of different time planes, such as process data generated in a cyclic interpolator time plane and a cyclic position control time plane, the process data for position control are accumulated over the time interval of an interpolation clock cycle and provided synchronously with the data of the interpolator for recording.

摘要翻译： 通过在延迟时间关键的循环时间平面（例如，主处理器时钟）中累积处理数据来记录处理数据，并且使用循环时钟将累积的数据存储在具有FIFO特性的数据缓冲存储器中。 数据缓冲存储器以延迟时间非关键非循环时间平面（例如，预处理时钟）读出，并且读出的数据被处理并作为数据集存储在日志存储器中。 为了实现诸如在循环内插器时间平面和循环位置控制时间平面中生成的处理数据的不同时间平面的处理数据的同步记录，用于位置控制的处理数据在内插时钟周期的时间间隔内被累积并提供 与用于记录的插值器的数据同步。

公开(公告)号：US3836891A

公开(公告)日：1974-09-17

申请号：US37648473

申请日：1973-07-05

申请人： BENDIX CORP

发明人： MC DANIEL G

IPC分类号： G06K7/016 ,  G05B19/408 ,  G06F5/10 ,  G06F5/14 ,  G06F11/10 ,  G06F7/00

CPC分类号： G06F5/14 ,  G05B19/408 ,  G05B2219/35366 ,  G06F11/1032

摘要： A tape reader system for numerical control systems including a segmented buffer memory into which characters are read from tape and stored sequentially. One address counter keeps track of ''''write'''' addresses and another counter keeps track of ''''read'''' addresses. The most significant digits of the two counters are compared to control the writing of fresh data into memory whenever the read address bears other than a selected proximity of the write address.

摘要翻译： 一种用于数字控制系统的磁带读取器系统，包括分段缓冲存储器，其中从磁带读取字符并顺序存储字符。 一个地址计数器跟踪“写入”地址，另一个计数器跟踪“读取”地址。 比较两个计数器的最高有效位，以便每当读取地址与写入地址的选定接近度以外时，将新鲜数据写入存储器。