公开(公告)号：US08737535B2

公开(公告)日：2014-05-27

申请号：US13248634

申请日：2011-09-29

Applicant: Ahmadreza (Reza) Rofougaran ,  Hooman Darabi

Inventor： Ahmadreza (Reza) Rofougaran ,  Hooman Darabi

IPC: H04L27/00

CPC classification number: H04B1/001 ,  H03H19/00 ,  H03H2015/007 ,  H04B1/0028

Abstract: A receiver includes an antenna interface, a frequency translation bandpass filter (FTBPF), a sample and hold module, and a down conversion module. The antenna interface is operable to receive a received wireless signal from an antenna structure and to isolate the received wireless signal from another wireless signal. The FTBPF is operable to filter the received wireless signal to produce an inbound wireless signal. The sample and hold module is operable to sample and hold the inbound wireless signal in accordance with an S&H clock signal to produce a frequency domain sample pulse train. The down conversion module is operable to convert the frequency domain sample pulse train into an inbound baseband signal.

Abstract translation: 接收机包括天线接口，频率转换带通滤波器（FTBPF），采样保持模块和下变频模块。 天线接口可操作以从天线结构接收接收到的无线信号，并将接收的无线信号与另一无线信号分离。 FTBPF可操作以对接收的无线信号进行滤波以产生入站无线信号。 采样和保持模块可操作以根据S＆H时钟信号采样和保持入站无线信号，以产生频域采样脉冲串。 下变频模块可操作以将频域采样脉冲串转换成入站基带信号。

公开(公告)号：US08385444B2

公开(公告)日：2013-02-26

申请号：US13241410

申请日：2011-09-23

Applicant: Ahmadreza (Reza) Rofougaran ,  Hooman Darabi

Inventor： Ahmadreza (Reza) Rofougaran ,  Hooman Darabi

IPC: H04K1/10 ,  H04L27/14

CPC classification number: H04B1/001 ,  H03H19/00 ,  H03H2015/007 ,  H04B1/0028

Abstract: A receiver includes a bandpass filter module, a sample and hold module, a discrete time bandpass filter module, a discrete time notch filter module, a combining module, and a conversion module. The bandpass filter module filters an inbound wireless that includes a desired signal component and an undesired signal component. The sample and hold module is operable to sample and hold the filtered inbound wireless signal to produce a frequency domain sample pulse train. The discrete time bandpass filter module bandpass filters the frequency domain sample pulse train to produce a bandpass filtered sample pulse. The discrete time notch filter module notch filters the frequency domain sample pulse train to produce a notched filtered sample pulse. The combining module combines the bandpass filtered sample pulse and the notched filtered sample pulse to produce a filtered inbound signal. The conversion module converts the filtered inbound signal into an inbound baseband signal.

Abstract translation: 接收机包括带通滤波器模块，采样和保持模块，离散时间带通滤波器模块，离散时间陷波滤波器模块，组合模块和转换模块。 带通滤波器模块对包括期望的信号分量和不期望的信号分量的入站无线电进行滤波。 采样和保持模块可操作以采样和保持滤波的入站无线信号以产生频域采样脉冲串。 离散时间带通滤波器模块对频域采样脉冲串进行滤波，以产生带通滤波采样脉冲。 离散时间陷波滤波器模块对频域采样脉冲串进行陷波滤波，以产生有缺口的滤波采样脉冲。 组合模块组合带通滤波的采样脉冲和带槽滤波的采样脉冲，以产生滤波的入站信号。 转换模块将滤波后的入站信号转换为入站基带信号。

公开(公告)号：US20130028359A1

公开(公告)日：2013-01-31

申请号：US13241400

申请日：2011-09-23

Applicant: AHMADREZA (REZA) ROFOUGARAN ,  HOOMAN DARABI

Inventor： AHMADREZA (REZA) ROFOUGARAN ,  HOOMAN DARABI

IPC: H04B1/10

CPC classification number: H04B1/001 ,  H03H19/00 ,  H03H2015/007 ,  H04B1/0028

Abstract: A receiver includes a sample and hold module, a discrete time filter module, and a conversion module. The sample and hold module includes a sample switching module, an impedance module, and a hold switching module. The sample switching module outputs samples of an inbound wireless signal in accordance with a sampling clock signal. The impedance module temporarily stores the samples. The hold switching module outputs a filtered representation of the samples in accordance with a hold clock signal to produce a frequency domain sample pulse train, wherein a filter response of the sample and hold module is in accordance with a ratio between the sampling clock signal and the hold clock signal. The discrete time filter module, which may be programmable, filters the frequency domain sample pulse train. The conversion module, which may be programmable, converts the filtered sample pulse into an inbound baseband signal.

Abstract translation: 接收机包括采样和保持模块，离散时间滤波器模块和转换模块。 采样和保持模块包括采样开关模块，阻抗模块和保持开关模块。 采样切换模块根据采样时钟信号输入入站无线信号的采样。 阻抗模块临时存储样品。 保持切换模块根据保持时钟信号输出采样的滤波表示，以产生频域采样脉冲序列，其中采样和保持模块的滤波器响应与采样时钟信号和 保持时钟信号。 可以编程的离散时间滤波器模块对频域采样脉冲串进行滤波。 可编程的转换模块将滤波的采样脉冲转换成入站基带信号。

公开(公告)号：US20130028349A1

公开(公告)日：2013-01-31

申请号：US13241469

申请日：2011-09-23

Applicant: AHMADREZA (REZA) ROFOUGARAN ,  HOOMAN DARABI

Inventor： AHMADREZA (REZA) ROFOUGARAN ,  HOOMAN DARABI

IPC: H04L25/49

CPC classification number: H04B1/001 ,  H03H19/00 ,  H03H2015/007 ,  H04B1/0028

Abstract: A transmitter includes a conversion module, a sample and hold module, and a discrete time bandpass filter module. The conversion module is operable to convert a first outbound baseband signal into a first outbound frequency domain pulse signal and to convert a second outbound baseband signal into a second outbound frequency domain pulse signal. The sample and hold module operable to sample and hold the first outbound frequency domain pulse signal and the second outbound frequency domain pulse signal to produce a frequency domain sample pulse train. The discrete time bandpass filter module is operable to filter the frequency domain sample pulse train to produce a first outbound wireless corresponding to the first baseband signal and to produce a second outbound wireless signal corresponding to the second inbound baseband signal.

Abstract translation: 发射机包括转换模块，采样和保持模块以及离散时间带通滤波器模块。 转换模块可操作以将第一出站基带信号转换为第一出站频域脉冲信号并将第二出站基带信号转换为第二出站频域脉冲信号。 采样和保持模块可操作以采样和保持第一出站频域脉冲信号和第二出站频域脉冲信号，以产生频域采样脉冲串。 离散时间带通滤波器模块可操作以对频域采样脉冲串进行滤波以产生对应于第一基带信号的第一出站无线电，并产生对应于第二入站基带信号的第二出站无线信号。

公开(公告)号：US20130028348A1

公开(公告)日：2013-01-31

申请号：US13241451

申请日：2011-09-23

Applicant: AHMADREZA (REZA) ROFOUGARAN ,  HOOMAN DARABI

Inventor： AHMADREZA (REZA) ROFOUGARAN ,  HOOMAN DARABI

IPC: H04L25/49

CPC classification number: H04B1/001 ,  H03H19/00 ,  H03H2015/007 ,  H04B1/0028

Abstract: A transmitter includes a conversion module, a sample and hold module, and a discrete time bandpass filter module. The conversion module is operable to convert an outbound baseband signal into outbound frequency domain pulse signal. The sample and hold module is operable to sample and hold the outbound frequency domain pulse signal to produce a frequency domain sample pulse train, wherein the sample and hold module is clocked at a rate corresponding to a frequency component of an outbound wireless signal. The discrete time bandpass filter module is operable to bandpass filter the frequency domain sample pulse train to produce the outbound wireless signal.

Abstract translation: 发射机包括转换模块，采样和保持模块以及离散时间带通滤波器模块。 转换模块可操作以将出站基带信号转换为出站频域脉冲信号。 采样和保持模块可操作以采样和保持出站频域脉冲信号以产生频域采样脉冲串，其中采样和保持模块以对应于出站无线信号的频率分量的速率被计时。 离散时间带通滤波器模块可用于对频域采样脉冲串进行带通滤波，以产生出站无线信号。

公开(公告)号：US20130028303A1

公开(公告)日：2013-01-31

申请号：US13248634

申请日：2011-09-29

Applicant: AHMADREZA (REZA) ROFOUGARAN ,  HOOMAN DARABI

Inventor： AHMADREZA (REZA) ROFOUGARAN ,  HOOMAN DARABI

IPC: H04L27/148 ,  H04B1/44

CPC classification number: H04B1/001 ,  H03H19/00 ,  H03H2015/007 ,  H04B1/0028

Abstract: A receiver includes an antenna interface, a frequency translation bandpass filter (FTBPF), a sample and hold module, and a down conversion module. The antenna interface is operable to receive a received wireless signal from an antenna structure and to isolate the received wireless signal from another wireless signal. The FTBPF is operable to filter the received wireless signal to produce an inbound wireless signal. The sample and hold module is operable to sample and hold the inbound wireless signal in accordance with an S&H clock signal to produce a frequency domain sample pulse train. The down conversion module is operable to convert the frequency domain sample pulse train into an inbound baseband signal.

Abstract translation: 接收机包括天线接口，频率转换带通滤波器（FTBPF），采样保持模块和下变频模块。 天线接口可操作以从天线结构接收接收到的无线信号，并将接收的无线信号与另一无线信号分离。 FTBPF可操作以对接收的无线信号进行滤波以产生入站无线信号。 采样和保持模块可操作以根据S＆H时钟信号采样和保持入站无线信号，以产生频域采样脉冲串。 下变频模块可操作以将频域采样脉冲串转换成入站基带信号。

公开(公告)号：US20130028302A1

公开(公告)日：2013-01-31

申请号：US13248562

申请日：2011-09-29

Applicant: AHMADREZA (REZA) ROFOUGARAN ,  HOOMAN DARABI

Inventor： AHMADREZA (REZA) ROFOUGARAN ,  HOOMAN DARABI

IPC: H04B1/38

CPC classification number: H04B1/001 ,  H03H19/00 ,  H03H2015/007 ,  H04B1/0028

Abstract: A discrete digital transceiver includes a receiver sample and hold module, a discrete digital receiver conversion module, a transmitter sample and hold module, a discrete digital transmitter conversion module, clock generation module, and a processing module. The receiver sample and hold module samples and holds an inbound wireless signal in accordance with a receiver S&H clock signal. The discrete digital receiver conversion module converts the receiver frequency domain sample pulse train into an inbound baseband signal. The transmitter sample and hold module samples and holds an outbound signal to produce a transmitter frequency domain sample pulse train. The discrete digital transmitter conversion module converts a transmitter frequency domain sample pulse train into the outbound wireless signal. The clock generation module generates S&H clock signals in accordance with a control signal. The processing module generates the control signal such that the S&H clock signals are shifted.

Abstract translation: 分立数字收发器包括接收机采样和保持模块，离散数字接收机转换模块，发射机采样和保持模块，分立数字发射机转换模块，时钟生成模块和处理模块。 接收机采样和保持模块根据接收机S＆H时钟信号采样并保存入站无线信号。 离散数字接收机转换模块将接收机频域采样脉冲串转换成入站基带信号。 发射机采样和保持模块采样并保存出站信号以产生发射机频域采样脉冲序列。 离散数字发射机转换模块将发射机频域采样脉冲串转换为出站无线信号。 时钟生成模块根据控制信号生成S＆H时钟信号。 处理模块产生控制信号，使得S＆H时钟信号被移位。

公开(公告)号：US20070064923A1

公开(公告)日：2007-03-22

申请号：US11509112

申请日：2006-08-23

Applicant: Bruce Schmukler ,  Arvind Raghavan ,  Ziba Nami ,  Jyothi Peddi ,  Andrew Kim ,  Michael Vrazel ,  Charles Summers

Inventor： Bruce Schmukler ,  Arvind Raghavan ,  Ziba Nami ,  Jyothi Peddi ,  Andrew Kim ,  Michael Vrazel ,  Charles Summers

IPC: H04M9/08

CPC classification number: H03H11/265 ,  H03H15/00 ,  H03H2015/007 ,  H04B3/23 ,  H04B3/238 ,  H04B3/32 ,  H04J1/12

Abstract: A circuit can process a sample of a signal to emulate, simulate, or model an effect on the signal. Thus, an emulation circuit can produce a representation of a real-world signal transformation by processing the signal according to one or more signal processing parameters that are characteristic of the real-world signal transformation. The emulation circuit can apply analog signal processing and/or mixed signal processing to the signal. The signal processing can comprise feeding the signal through two signal paths, each having a different delay, and creating a weighted sum of the outputs of the two signal paths. The signal processing can also (or alternatively) comprise routing the signal through a network of delay elements, wherein a bank of switching or routing elements determines the route and thus the resulting delay.

Abstract translation: 电路可以处理信号的样本以对信号进行仿真，模拟或建模。 因此，仿真电路可以通过根据作为真实世界信号变换的特征的一个或多个信号处理参数处理信号来产生现实世界信号变换的表示。 仿真电路可以对信号应用模拟信号处理和/或混合信号处理。 信号处理可以包括通过两个信号路径馈送信号，每个信号路径具有不同的延迟，并且产生两个信号路径的输出的加权和。 信号处理还可以（或者可选地）包括通过延迟元件的网络路由信号，其中一组交换或路由元件确定路由并且因此确定所得到的延迟。

公开(公告)号：US20050015419A1

公开(公告)日：2005-01-20

申请号：US10619771

申请日：2003-07-14

Applicant: Chiang Pu ,  Scott Chiu ,  Yonghui Tang

Inventor： Chiang Pu ,  Scott Chiu ,  Yonghui Tang

IPC: G06F17/10 ,  H03H15/02

CPC classification number: H03H15/02 ,  H03H2015/007

Abstract: Briefly, a finite impulse response filter to generating coefficients having a programmable magnitude and quantum tunability.

Abstract translation: 简而言之，有限脉冲响应滤波器用于产生具有可编程幅度和量子可调性的系数。

公开(公告)号：US09325302B1

公开(公告)日：2016-04-26

申请号：US14558851

申请日：2014-12-03

Applicant: Lattice Semiconductor Corporation

Inventor： Vinh Ho ,  Magathi Jayaram ,  David Wei

IPC: H03K5/00 ,  H03K5/1252 ,  H03H11/04

CPC classification number: H03K5/1252 ,  H03H15/00 ,  H03H17/0294 ,  H03H17/06 ,  H03H2015/007

Abstract: In several embodiments of the invention, a programmable architecture for FIR filters includes a tapped delay chain and a number of different slices. Each slice has a multiplexer that receives all of the tapped input-signal samples and a programmable current driver. Each slice can be independently programmed to correspond to any one of the taps in the delay chain, such that zero, one, or more slices can be associated with any of the delay-chain taps. Moreover, the current driver in each slice can be independently programmed to contribute any available driver strength level for the selected tap, where the combination of one or more drive strengths associated with a given tap corresponds to the effective tap coefficient for that tap. In this way, the architecture can be programmed to provide a variety of different filters having not just transfer functions with different coefficient values, but also transfer functions having different numbers of pre-cursor and/or post-cursor taps.

Abstract translation: 在本发明的若干实施例中，用于FIR滤波器的可编程架构包括抽头延迟链和多个不同切片。 每个切片具有接收所有抽头输入信号样本和可编程电流驱动器的多路复用器。 每个切片可以被独立地编程以对应于延迟链中的任何一个抽头，使得零，一个或多个切片可以与任何延迟链抽头相关联。 此外，每个切片中的当前驱动器可以被独立地编程以为所选择的抽头提供任何可用的驱动器强度级别，其中与给定抽头相关联的一个或多个驱动强度的组合对应于该抽头的有效抽头系数。 以这种方式，可以对该体系结构进行编程，以提供不仅具有不同系数值的传递函数的各种不同的滤波器，而且还具有具有不同数量的前置光标和/或后置光标抽头的传输函数。