公开(公告)号：US06731683B1

公开(公告)日：2004-05-04

申请号：US09677269

申请日：2000-10-02

申请人： Alan S. Fiedler ,  Brett D. Hardy

发明人： Alan S. Fiedler ,  Brett D. Hardy

IPC分类号： H03H730

CPC分类号： H04L25/03159 ,  H04L1/203 ,  H04L7/0058 ,  H04L7/0331 ,  H04L2025/03738

摘要： A serial data communication receiver includes a serial data input, first and second equalizers, first and second capture latch circuits, and an equalization control circuit. The first and second equalizers are coupled to the serial data input and have first and second equalized serial data outputs, respectively. Each equalizer has a frequency response that is variable over a range of frequency response settings. The first and second capture latch circuits are coupled to the first and second equalized serial data outputs, respectively, in a phase-locked loop and have first and second recovered data outputs, respectively. The equalization control circuit measures a data eye size of the second equalized serial data output over the range of frequency response settings of the second equalizer and sets the frequency response of the first equalizer to one of the frequency response settings based on the measured data eye sizes.

摘要翻译： 串行数据通信接收机包括串行数据输入，第一和第二均衡器，第一和第二捕捉锁存电路以及均衡控制电路。 第一和第二均衡器耦合到串行数据输入端，分别具有第一和第二均衡串行数据输出。 每个均衡器具有频率响应，频率响应在频率响应设置的范围内是可变的。 第一和第二捕捉锁存电路分别在锁相环中耦合到第一和第二均衡的串行数据输出，并且分别具有第一和第二恢复的数据输出。 均衡控制电路测量第二均衡器的频率响应设置范围上的第二均衡串行数据输出的数据眼尺寸，并且基于所测量的数据眼尺寸将第一均衡器的频率响应设置为频率响应设置之一 。