公开(公告)号：US06490325B1

公开(公告)日：2002-12-03

申请号：US09164245

申请日：1998-09-30

申请人： Alan S. Fiedler ,  Michael O. Jenkins

发明人： Alan S. Fiedler ,  Michael O. Jenkins

IPC分类号： H04B300

CPC分类号： H03H7/38

摘要： A data transmission circuit for transmitting a data stream includes a voltage supply terminal, a resistively terminated, controlled-impedance transmission line and an inductor coupled between the voltage supply terminal and the controlled-impedance transmission line.

摘要翻译： 用于发送数据流的数据传输电路包括电压供给端子，电阻端接的受控阻抗传输线和耦合在电压提供端子和受控阻抗传输线之间的电感器。

公开(公告)号：US5854575A

公开(公告)日：1998-12-29

申请号：US969100

申请日：1997-11-13

申请人： Alan S. Fiedler ,  Daniel J. Baxter

发明人： Alan S. Fiedler ,  Daniel J. Baxter

IPC分类号： H03L7/093 ,  H03L7/107 ,  H03L7/08

CPC分类号： H03L7/093 ,  H03L7/107

摘要： An integrated circuit phase-locked loop includes a phase/frequency detector, a charge pump, and a voltage-controlled oscillator (VCO) which are coupled together in series. The VCO has first and second VCO control inputs, and has a VCO output which is coupled to the phase/frequency detector. An off-chip loop filter input is coupled between the charge pump and the first VCO control input for coupling to an off-chip loop filter. An on-chip loop filter is coupled between the first VCO control input and the second VCO control input. The VCO has a lower voltage-to-frequency gain from the first VCO control input to the VCO output than from the second VCO control input to the VCO output.

摘要翻译： 集成电路锁相环包括串联耦合在一起的相/频检波器，电荷泵和压控振荡器（VCO）。 VCO具有第一和第二VCO控制输入，并且具有耦合到相位/频率检测器的VCO输出。 片外环路滤波器输入耦合在电荷泵和第一VCO控制输入端之间，用于耦合到片外环路滤波器。 片上环路滤波器耦合在第一VCO控制输入端和第二VCO控制输入端之间。 VCO从第一个VCO控制输入到VCO输出的电压 - 频率增益较低，而不是从VCO输出的第二个VCO控制输入。

公开(公告)号：US5805089A

公开(公告)日：1998-09-08

申请号：US734691

申请日：1996-10-21

申请人： Alan S. Fiedler ,  Shoba Krishnan

发明人： Alan S. Fiedler ,  Shoba Krishnan

IPC分类号： H03M9/00

CPC分类号： H03M9/00

摘要： A time-division data multiplexer has feedback for adjusting the select clock cross-over voltage. The multiplexer includes a multi-phase clock generator having a plurality of select clock outputs with different phases, a plurality of parallel data inputs and first and second serial data outputs. A first set of gating transistors is coupled between the first data output and a common node. Each transistor in the first set is gated by a corresponding data input and at least one corresponding select clock output. A second set of gating transistors is coupled between the second data output and the common node. Each transistor in the second set is gated by a corresponding data input and at least one corresponding select clock output. A first current source is coupled to the common node. An amplifier has a first input which is coupled to the common node, a second input which is coupled to a reference voltage generator and a cross-over control output which is coupled to the plurality of select clock outputs for adjusting the cross-over voltage of the select clock outputs in response to a comparison of the voltages on the first and second amplifier inputs. A loop filter is coupled to the cross-over control output.

摘要翻译： 时分数据多路复用器具有用于调整选择时钟交叉电压的反馈。 多路复用器包括具有多个具有不同相位的选择时钟输出的多相时钟发生器，多个并行数据输入和第一和第二串行数据输出。 第一组选通晶体管耦合在第一数据输出和公共节点之间。 第一组中的每个晶体管由对应的数据输入和至少一个对应的选择时钟输出选通。 第二组选通晶体管耦合在第二数据输出和公共节点之间。 第二组中的每个晶体管由对应的数据输入和至少一个对应的选择时钟输出选通。 第一电流源耦合到公共节点。 放大器具有耦合到公共节点的第一输入端，耦合到参考电压发生器的第二输入端和耦合到多个选择时钟输出的交叉控制输出端，用于调整交叉电压 所述选择时钟输出响应于所述第一和第二放大器输入端的电压的比较。 环路滤波器耦合到交叉控制输出。

公开(公告)号：US4970413A

公开(公告)日：1990-11-13

申请号：US113944

申请日：1987-10-28

申请人： Richard C. Eden ,  John E. Clark ,  Alan S. Fiedler ,  Frank S. Lee ,  Robert Miller

发明人： Richard C. Eden ,  John E. Clark ,  Alan S. Fiedler ,  Frank S. Lee ,  Robert Miller

IPC分类号： H03K5/003 ,  G05F3/24 ,  H03K19/003 ,  H03K19/0185 ,  H03K19/0952

CPC分类号： H03K19/00384 ,  G05F3/245 ,  G05F3/247 ,  H03K19/018535

摘要： A V.sub.BB input threshold potential with feedback circuitry is used to stabilize all of the logic inputs on an GaAs IC to ECL compatible levels over a normal temperature range and normal power supply variations. The system called "V.sub.BB -Feedback" uses "zero translation delay" direct Capacitor Diode Fet Logic (CDFL) inputs. This is an extension of the CDFL circuit approach in which the voltage across the input level shift circuitry on all inputs is adjusted to maintain a threshold voltage equal to the dc potential on an "extra" V.sub.BB input in spite of variations of temperature, power supply voltages or processing parameters such as MESFET pinchoff voltage. A dc potential (V.sub.BB) is applied to the "extra" V.sub.BB input, which is an additional input that is essentially identical to the actual logic inputs. All of the logic input threshold voltages are then slaved to the V.sub.BB dc potential applied to the "extra" V.sub.BB input. ECL compatability is accomplished by combining a reasonably compliant, but uniform, CDFL voltage shifter with feedback circuitry to maintain the shift voltages at proper levels thereby achieving the desired input logic threshold.

公开(公告)号：US06181157B2

公开(公告)日：2001-01-30

申请号：US08967150

申请日：1997-11-10

申请人： Alan S. Fiedler

发明人： Alan S. Fiedler

IPC分类号： H03K1716

CPC分类号： H04L25/0278 ,  H04L25/0272

摘要： A circuit that provides a termination resistance to a transmission line includes a controllable termination resistor coupled between the transmission line and a termination voltage node. The circuit also includes a control circuit coupled to the controllable termination resistor and to a reference resistor. The control circuit matches the resistance of the controllable termination resistor to the resistance of the reference resistor.

摘要翻译： 提供对传输线路的终端电阻的电路包括耦合在传输线路和终端电压节点之间的可控终端电阻器。 电路还包括耦合到可控终端电阻器和参考电阻器的控制电路。 控制电路将可控终端电阻的电阻与参考电阻的电阻相匹配。

公开(公告)号：US20090322388A1

公开(公告)日：2009-12-31

申请号：US12163008

申请日：2008-06-27

申请人： Alan S. Fiedler

发明人： Alan S. Fiedler

IPC分类号： H03L7/06

CPC分类号： H03L7/0812 ,  H03L7/07 ,  H03L7/085

摘要： A multi-phase correction circuit adjusts the phase relationship among multiple clock signals such that their rising edges are equidistant in time from one another.

摘要翻译： 多相校正电路调节多个时钟信号之间的相位关系，使得它们的上升沿彼此等距。

公开(公告)号：US06701466B1

公开(公告)日：2004-03-02

申请号：US09677350

申请日：2000-10-02

申请人： Alan S. Fiedler

发明人： Alan S. Fiedler

IPC分类号： G06K504

CPC分类号： H03L7/081 ,  H03L7/0891 ,  H03L7/091 ,  H03L7/0995 ,  H04L7/0037 ,  H04L7/033

摘要： A serial data communication receiver includes a serial data input and first and second sets of data capture latches, which are coupled to the serial data input and have first and second recovered data outputs, respectively. One of the sets is designated as a master set and the other a slave set. Each data capture latch has a respective independently adjustable offset voltage. An offset adjustment control circuit varies the respective offset voltage over a range of offset voltage values for each of the data capture latches in the slave set while comparing the first and second recovered data outputs to produce an error output. The control circuit then sets each of the respective offset voltages in the slave set to one of the offset voltage values based on the error output.

摘要翻译： 串行数据通信接收机包括串行数据输入以及耦合到串行数据输入的第一和第二组数据捕获锁存器，并分别具有第一和第二恢复数据输出。 其中一个集合被指定为主集，另一个被指定为从集。 每个数据捕获锁存器具有各自独立可调的失调电压。 偏移调整控制电路在比较第一和第二恢复数据输出以产生误差输出时，在从属组中的每个数据捕获锁存器的偏移电压值的范围上改变各个偏移电压。 然后，控制电路基于错误输出将从设定中的各偏移电压中的每一个设置为偏移电压值之一。

公开(公告)号：US6114982A

公开(公告)日：2000-09-05

申请号：US105702

申请日：1998-06-26

申请人： Brett D. Hardy ,  Alan S. Fiedler

发明人： Brett D. Hardy ,  Alan S. Fiedler

IPC分类号： H03M1/06 ,  H03M1/36

CPC分类号： H03M1/0682 ,  H03M1/365

摘要： An analog-to-digital (A/D) converter for converting an analog signal into a digital signal includes a first resistor ladder coupled between a first reference voltage and a second reference voltage. The A/D converter also includes a second resistor ladder that matches the first resistor ladder and that has a first end and a second end coupled to an analog signal source. The first resistor ladder and the second resistor ladder are coupled to at least two comparators with each comparator having a reference input and an analog input. The impedance at each reference input due to the first resistor ladder matches the impedance at each corresponding analog input due to the second resistor ladder.

摘要翻译： 用于将模拟信号转换为数字信号的模数（A / D）转换器包括耦合在第一参考电压和第二参考电压之间的第一电阻器梯形。 A / D转换器还包括与第一电阻梯相匹配的第二电阻梯，其具有耦合到模拟信号源的第一端和第二端。 第一电阻梯和第二电阻梯耦合到至少两个比较器，每个比较器具有参考输入和模拟输入。 由于第一个电阻梯形图，每个参考输入端的阻抗与每个相应的模拟输入端的阻抗相匹配，这是由于第二个电阻梯。

公开(公告)号：US6054903A

公开(公告)日：2000-04-25

申请号：US969275

申请日：1997-11-13

申请人： Alan S. Fiedler

发明人： Alan S. Fiedler

IPC分类号： H03L7/089 ,  H03L7/093 ,  H03L7/099 ,  H03L7/107 ,  H03L7/183 ,  H03L7/08

CPC分类号： H03L7/0891 ,  H03L7/099 ,  H03L7/107 ,  H03L2207/06 ,  H03L7/093 ,  H03L7/183

摘要： A phase-locked loop fabricated on an integrated circuit includes a phase/frequency detector, a charge pump, a filter node and a voltage-controlled oscillator (VCO) which are coupled together in series. The VCO has first and second frequency control inputs and a VCO output, wherein the first frequency control input is coupled to the filter node and the VCO output is coupled to the phase/frequency detector. The VCO has a first voltage-to-frequency gain from the first frequency control input to the VCO output and a second voltage-to-frequency gain from the second frequency control input to the VCO output. An off-chip filter input is coupled to the filter node for coupling to an off-chip loop filter. An on-chip loop filter is coupled between the first frequency control input and the second frequency control input and has a variable time constant. A time constant control circuit is coupled to the on-chip loop filter for controlling the variable time constant.

摘要翻译： 在集成电路上制造的锁相环包括串联耦合在一起的相位/频率检测器，电荷泵，滤波器节点和压控振荡器（VCO）。 VCO具有第一和第二频率控制输入和VCO输出，其中第一频率控制输入耦合到滤波器节点，并且VCO输出耦合到相位/频率检测器。 VCO具有从第一频率控制输入到VCO输出的第一电压 - 频率增益和从第二频率控制输入到VCO输出的第二电压 - 频率增益。 片外滤波器输入耦合到滤波器节点以耦合到片外环路滤波器。 片上环路滤波器耦合在第一频率控制输入端和第二频率控制输入端之间，具有可变的时间常数。 时间常数控制电路耦合到片上环路滤波器，用于控制可变时间常数。

公开(公告)号：US5955978A

公开(公告)日：1999-09-21

申请号：US925041

申请日：1997-09-08

申请人： Alan S. Fiedler ,  Brett D. Hardy

发明人： Alan S. Fiedler ,  Brett D. Hardy

IPC分类号： H03M1/10 ,  H03M1/12

CPC分类号： H03M1/1023 ,  H03M1/12

摘要： An A/D converter has an auto-zeroed latching comparator with an input offset voltage. The latching comparator is repetitively switched between an offset adjustment mode and a conversion mode. When the comparator is in the offset adjustment mode, the comparator compares the reference voltage to itself and generates an offset measurement output based on the comparison. A feedback circuit adjusts the input offset voltage based on the offset measurement output. When the comparator is in the conversion mode, the comparator compares the input signal to the reference voltage and generates the digital output signal based on the comparison.

摘要翻译： A / D转换器具有自动归零锁存比较器，具有输入失调电压。 锁存比较器在偏移调整模式和转换模式之间重复切换。 当比较器处于偏移调整模式时，比较器将参考电压与其自身进行比较，并根据比较产生偏移测量输出。 反馈电路根据偏移测量输出调整输入失调电压。 当比较器处于转换模式时，比较器将输入信号与参考电压进行比较，并根据比较产生数字输出信号。