公开(公告)号：US20040268332A1

公开(公告)日：2004-12-30

申请号：US10829205

申请日：2004-04-22

发明人： Masato Mitsumori ,  Kei Nakajima ,  Satoshi Iesaka

IPC分类号： G06F009/45

CPC分类号： G06F12/1416

摘要： An invalid memory access detection program early detects invalid memory access caused by a program operating in a system in which memory access can be freely performed, said program being called from a program operating in a system in which invalid memory access does not occur. An execution program of the Java VM executes a Java byte code that has been read. A native method library execution module calls a native method library, and executes it. During or after the execution of the native method library, an invalid memory access detection module checks a memory area reserved by the memory reservation module, and thereby detects invalid memory access caused by the native method library.

公开(公告)号：US20040268331A1

公开(公告)日：2004-12-30

申请号：US10625892

申请日：2003-07-22

申请人： Microsoft Corporation

发明人： Charles L. Mitchell ,  Julian Burger ,  Vinod K. Grover ,  David Read Tarditi JR.

IPC分类号： G06F009/45

摘要： Various intermediate representation techniques for software development tool scenarios are described. An intermediate representation format can be used for both high level and low level representations. The intermediate representation can be built from various operands and instructions types. Various annotations can be added to the intermediate representation without modifying its format. For example, flow control and data control can be explicitly represented by threading a graph through the intermediate representation.

摘要翻译： 描述了用于软件开发工具场景的各种中间表示技术。 中间表示格式可用于高级和低级表示。 中间表示可以由各种操作数和指令类型构建。 可以将各种注释添加到中间表示，而不修改其格式。 例如，流控制和数据控制可以通过中间表示线图来显式表示。

公开(公告)号：US20040268328A1

公开(公告)日：2004-12-30

申请号：US10607601

申请日：2003-06-27

申请人： Microsoft Corporation

发明人： Mark Ronald Plesko ,  David Read Tarditi JR.

IPC分类号： G06F009/45

CPC分类号： G06F8/437

摘要： A representation of types, type-checker, and compiler are provided for checking consistency in various forms of an intermediate language. Type-checking a programming language in a compiler is accomplished by taking one or more rule sets as input to a type-checker, which selects one or more of the rule sets based upon any one, or combination of two or more, of numerous criteria. Among them are stage of compilation, source language, architecture, and level of typing present in the language being type-checked. The language is then type-checked using the selected one or more rule sets. The rule sets can include one rule set corresponding to strong type-checking, one rule set corresponding to weak type-checking, and one rule set corresponding to representation type-checking. In the alternative, a compiler can be provided with a type-checker that constructs the one or more sets of rules at runtime from a larger set of rules based on any one, or combination of two or more, of the previously mentioned criteria.

摘要翻译： 提供了类型，类型检查器和编译器的表示，用于检查中间语言的各种形式的一致性。 通过将一个或多个规则集作为输入来检查编译器中的编程语言来实现类型检查器，该类型检查器基于许多标准中的任何一个或两个或更多个的组合来选择一个或多个规则集 。 其中包括编译阶段，源语言，架构以及正在类型检查语言中的打字级别。 然后使用所选的一个或多个规则集对该语言进行类型检查。 规则集可以包括对应于强类型检查的一个规则集，对应于弱类型检查的一个规则集，以及对应于表示类型检查的一个规则集。 在替代方案中，可以向编译器提供类型检查器，该类型检查器基于上述标准中的任何一个或两个或更多个的组合从更大的规则集合在运行时构建一组或多组规则。

公开(公告)号：US20040268323A1

公开(公告)日：2004-12-30

申请号：US10875303

申请日：2004-06-25

申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD

发明人： Hirohisa Tanaka ,  Kensuke Odani ,  Akira Tanaka

IPC分类号： G06F009/45

CPC分类号： G06F8/443 ,  G06F9/4488

摘要： According to program converting step S100 of the present invention, classes whose objects are created out of the classes included in a program are detected and the result is recorded in an analysis information storing section 12 at an object analyzing step S104, functions (unnecessary functions) regarding classes whose objects are not created are analyzed in accordance with information held in the analysis information storing section 12 and the result is recorded in the analysis information storing section 12 at an unnecessary function analyzing step S105, and definitions of the unnecessary functions are deleted in accordance with information held in the analysis information storing section 12 at an unnecessary function deleting step S106.

摘要翻译： 根据本发明的程序转换步骤S100，在对象分析步骤S104中，检测在包含在程序中的类别中创建的对象的类别，并将结果记录在分析信息存储部分12中，功能（不必要的功能） 关于根据分析信息存储部分12中保存的信息来分析对象未被创建的类别，并且在不必要的功能分析步骤S105将结果记录在分析信息存储部分12中，并且删除不必要的功能的定义 根据在不必要的功能删除步骤S106中保存在分析信息存储部分12中的信息。

公开(公告)号：US20040268279A1

公开(公告)日：2004-12-30

申请号：US10602937

申请日：2003-06-24

申请人： LSI LOGIC CORPORATION

发明人： Nicholas A. Oleksinski ,  Michael A. Minter

IPC分类号： G06F009/45

CPC分类号： G06F17/5045 ,  G06F2217/62

摘要： A method for generating a plurality of timing constraints for a circuit design is disclosed. The method generally includes the steps of (A) identifying a plurality of clock signals by analyzing the circuit design, (B) determining a plurality of relationships among the clock signals and (C) generating the timing constraints for the circuit design in response to the clock signals and the relationships.

公开(公告)号：US20040267514A1

公开(公告)日：2004-12-30

申请号：US10604179

申请日：2003-06-30

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Kerry Bernstein ,  Philip G. Emma ,  Leendert M. Huisman ,  Paul D. Kartschoke ,  Norman J. Rohrer

IPC分类号： G06F009/45 ,  G06F017/50

CPC分类号： G06F17/5022

摘要： A method and system for simulating an integrated circuit. The method includes the steps of performing a timing analysis of the circuits to ensure that they meet specified timing criteria, performing soft error analysis of the circuits to determine whether they meet specified soft error criteria, and improving those circuits that fail the soft error analysis to improve their resistance to soft errors and having no degradation on timing. Preferably, the improving step includes the step of improving those circuits that fail the soft error analysis by either having an additional voltage source or altering the capacitance of the circuits.

公开(公告)号：US20040261069A1

公开(公告)日：2004-12-23

申请号：US10600906

申请日：2003-06-20

申请人： Sun Microsystems, Inc.

发明人： Jerome M. Verbeke ,  Neelakanth M. Nadgir

IPC分类号： G06F009/44 ,  G06F009/45 ,  G06F009/46

CPC分类号： G06F9/44521

摘要： System and method for dynamic loading of remote classes. Using embodiments, remote classes may be loaded dynamically by a default class loader without the use of separate, custom class loaders. The remote class loader mechanism may locate on remote systems classes needed by code executing on the local system but not locally stored, and which therefore cannot be located and loaded by the default class loader. After locating the classes, the remote class loader mechanism may obtain copies of the classes and save them to a location indicated by the class path of the default class loader. The default class loader can then locate and load the classes from the location indicated by the class path.

摘要翻译： 用于动态加载远程类的系统和方法。 使用实施例，远程类可以由默认的类加载器动态地加载，而不使用单独的定制类加载器。 远程类加载器机制可能定位在本地系统上执行的代码所需的远程系统类上，但不能在本地存储，因此无法由默认的类加载器找到并加载它们。 定位类后，远程类加载器机制可以获取类的副本并将其保存到默认类加载器的类路径指示的位置。 默认类加载器可以从类路径指示的位置找到并加载类。

公开(公告)号：US20040261058A1

公开(公告)日：2004-12-23

申请号：US10739876

申请日：2003-12-17

发明人： Kenneth S. Kundert

IPC分类号： G06F009/44 ,  G06F009/45

CPC分类号： G06F13/105 ,  G01R31/318357 ,  G01R31/318364 ,  G06F11/261 ,  G06F17/50 ,  G06F17/5009 ,  G06F17/5022 ,  G06F17/5036

摘要： A method and mechanism for implementing a general purpose scripting language that supports parallel execution is described. In one approach, parallel execution is provided in a seamless and high-level approach rather than requiring or expecting a user to have low-level programming expertise with parallel processing languages/functions. Also described is a system and method for performing circuit simulation. The present approach provides methods and systems that create reusable and independent measurements for use with circuit simulators. Also disclosed are parallelizable measurements having looping constructs that can be run without interference between parallel iterations. Reusability is enhanced by having parameterized measurements. Revisions and history of the operating parameters of circuit designs subject to simulation are tracked.

摘要翻译： 描述了一种用于实现支持并行执行的通用脚本语言的方法和机制。 在一种方法中，以无缝和高级方法提供并行执行，而不是要求或期望用户具有并行处理语言/功能的低级编程专长。 还描述了一种用于执行电路仿真的系统和方法。 本方法提供了创建可重复使用和独立测量以用于电路模拟器的方法和系统。 还公开了具有循环结构的可并行测量，其可以在并行迭代之间不受干扰地运行。 通过参数化测量可以提高可重用性。 跟踪仿真电路设计的工作参数的修改和历史。

公开(公告)号：US20040261055A1

公开(公告)日：2004-12-23

申请号：US10660353

申请日：2003-09-11

发明人： P. Anders I. Bertelrud ,  Theodore C. Goldstein

IPC分类号： G06F009/44 ,  G06F009/45

CPC分类号： G06F8/41 ,  G06F8/71

摘要： A method and apparatus are provided for predictively processing tasks for building software. The method comprises initiating compilation of a file in a processor-based system in advance of a request from a user to compile the file, detecting the user request to compile the file and indicating a status of the compilation of the file in response to detecting the user request.

摘要翻译： 提供了用于预测性地处理用于构建软件的任务的方法和装置。 该方法包括在来自用户的编译文件的请求之前启动基于处理器的系统中的文件的编译，检测用户请求编译文件并响应于检测到文件而指示文件的编译状态 用户请求。

公开(公告)号：US20040261045A1

公开(公告)日：2004-12-23

申请号：US10463282

申请日：2003-06-17

申请人： INTERNATIONAL BUSSINESS MACHINES CORPORATION

发明人： Paul Eric Dahlen ,  Roger John Gravrok ,  David Loren Heckmann ,  Mark Owen Maxson

IPC分类号： G06F009/45 ,  G06F017/50

CPC分类号： G06F17/5036

摘要： A method, apparatus, system, and signal-bearing medium that in an embodiment select a subset of transmission line models based on bounding electrical criteria. The bounding electrical criteria may include combinations of maximum and minimum values and in an embodiment may also include nominal values. Models that meet the bounding electrical criteria may be used in modeling the transmission line while models that do not meet the bounding electrical criteria are not used.

摘要翻译： 一种方法，装置，系统和信号承载介质，其在一个实施例中基于边界电标准选择传输线模型的子集。 有界电气标准可以包括最大值和最小值的组合，并且在实施例中也可以包括标称值。 符合有界电气标准的模型可用于对传输线进行建模，而不使用不符合有界电气标准的模型。