公开(公告)号：US20040136436A1

公开(公告)日：2004-07-15

申请号：US10339992

申请日：2003-01-10

申请人： International Business Machines Corporation

发明人： Herschel Ainspan ,  Philip G. Emma ,  Rick A. Rand ,  Arthur R. Zingher

IPC分类号： G01K013/00

CPC分类号： G01K1/028 ,  G01K7/42 ,  G01K2219/00

摘要： This invention relates to digitally measuring operating parameters, for example, temperature, within a semiconductor chip and making those measurements internally available to hardware, firmware, and software.

摘要翻译： 本发明涉及数字测量半导体芯片内的操作参数，例如温度，并且使这些测量在内部可用于硬件，固件和软件。

公开(公告)号：US20040267514A1

公开(公告)日：2004-12-30

申请号：US10604179

申请日：2003-06-30

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Kerry Bernstein ,  Philip G. Emma ,  Leendert M. Huisman ,  Paul D. Kartschoke ,  Norman J. Rohrer

IPC分类号： G06F009/45 ,  G06F017/50

CPC分类号： G06F17/5022

摘要： A method and system for simulating an integrated circuit. The method includes the steps of performing a timing analysis of the circuits to ensure that they meet specified timing criteria, performing soft error analysis of the circuits to determine whether they meet specified soft error criteria, and improving those circuits that fail the soft error analysis to improve their resistance to soft errors and having no degradation on timing. Preferably, the improving step includes the step of improving those circuits that fail the soft error analysis by either having an additional voltage source or altering the capacitance of the circuits.

公开(公告)号：US20040221185A1

公开(公告)日：2004-11-04

申请号：US10428170

申请日：2003-05-01

申请人： International Business Machines Corporation

发明人： Pradip Bose ,  David M. Brooks ,  Peter W. Cook ,  Philip G. Emma ,  Michael K. Gschwind ,  Stanley E. Schuster ,  Vijayalakshmi Srinivasan

IPC分类号： G06F001/26

CPC分类号： G06F9/3869 ,  G06F1/3203 ,  G06F1/3243 ,  G06F1/3246 ,  G06F1/3287 ,  Y02D10/152 ,  Y02D10/171

摘要： An integrated circuit (IC) including unit power control, leakage reduction circuit for controllably reducing leakage power with reduced LdI/dt noise in the IC and, an activity prediction unit invoking active/dormant states in IC units. The prediction unit determines turn on and turn off times for each IC unit. The prediction unit controls a supply voltage select circuit selectively passing a supply voltage to a separate supply line at the predicted turn on time and selectively blocking the supply voltage at the predicted turn off time.

摘要翻译： 包括单元功率控制的集成电路（IC），用于可控地减少IC中的LdI / dt噪声的泄漏功率的泄漏降低电路，以及在IC单元中调用主动/休眠状态的活动预测单元。 预测单元确定每个IC单元的导通和关闭时间。 预测单元控制电源电压选择电路，其在预测的导通时间选择性地将电源电压传递到单独的电源线，并且在预测的关断时间选择性地阻断电源电压。

公开(公告)号：US20040105648A1

公开(公告)日：2004-06-03

申请号：US10307951

申请日：2002-12-02

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Cameron J. Brooks ,  Philip G. Emma ,  Casimer M. DeCusatis ,  Lawrence Jacobowitz ,  John U. Knickerbocker

IPC分类号： G02B006/36

CPC分类号： G02B6/3636 ,  G02B6/3608 ,  G02B6/3652 ,  G02B6/3676 ,  G02B6/43

摘要： A ferrule-less optical backplane connector assembly includes a substrate having at least a pair of optical guide receiving structures formed therein, the pair of optical guide receiving structures further being formed at substantially a right angle with respect to one another so as to guide a corresponding first and second optical guide into optical alignment with one another.

公开(公告)号：US20040041590A1

公开(公告)日：2004-03-04

申请号：US10064921

申请日：2002-08-29

申请人： International Business Machines Corporation

发明人： Kerry Bernstein ,  Philip G. Emma ,  John A. Fifield ,  Paul D. Kartschoke ,  Norman J. Rohrer ,  Peter A. Sandon

IPC分类号： H03K019/096

CPC分类号： H03K19/0963 ,  H03K19/00338

摘要： An integrated circuit that includes a dynamic logic gate having an output node at which a logical output value of the logic gate is detected and also includes a circuit for selectable alteration of the soft error susceptibility of the dynamic logic gate.

摘要翻译： 一种集成电路，其包括具有输出节点的动态逻辑门，在该输出节点检测逻辑门的逻辑输出值，并且还包括用于可选择地改变动态逻辑门的软错误敏感性的电路。

公开(公告)号：US20040015683A1

公开(公告)日：2004-01-22

申请号：US10197714

申请日：2002-07-18

申请人： International Business Machines Corporation

发明人： Philip G. Emma ,  Klaus J. Getzlaff ,  Allan M. Hartstein ,  Thomas Pflueger ,  Thomas R. Puzak ,  Eric Mark Schwarz ,  Vijayalakshmi Srinivasan

IPC分类号： G06F009/00

CPC分类号： G06F9/3806

摘要： A two level branch history table (TLBHT) is substantially improved by providing a mechanism to prefetch entries from the very large second level branch history table (L2 BHT) into the active (very fast) first level branch history table (L1 BHT) before the processor uses them in the branch prediction process and at the same time prefetch cache misses into the instruction cache. The mechanism prefetches entries from the very large L2 BHT into the very fast L1 BHT before the processor uses them in the branch prediction process. A TLBHT is successful because it can prefetch branch entries into the L1 BHT sufficiently ahead of the time the entry is needed. This feature of the TLBHT is also used to prefetch instructions into the cache ahead of their use. In fact, the timeliness of the prefetches produced by the TLBHT can be used to remove most of the cycle time penalty incurred by cache misses.

摘要翻译： 通过提供一种将超大型第二级分支历史表（L2 BHT）中的条目预取到活动（非常快）的第一级分支历史表（L1 BHT）中的条目之前，两级分支历史表（TLBHT）被大大改善 处理器在分支预测过程中使用它们，并且同时将高速缓存未命中预取到指令高速缓存中。 在处理器在分支预测过程中使用它们之前，该机制将从非常大的L2 BHT中将条目预取到非常快的L1 BHT中。 TLBHT是成功的，因为它可以在需要输入的时间之前将分支条目预取到L1 BHT中。 TLBHT的这个功能也用于在使用之前将指令预取到高速缓存中。 实际上，由TLBHT产生的预取的及时性可以用来消除高速缓存未命中引起的大部分周期时间损失。