公开(公告)号：US5732254A

公开(公告)日：1998-03-24

申请号：US783039

申请日：1997-01-14

申请人： Kyoko Tanimoto ,  Aiichiro Inoue

发明人： Kyoko Tanimoto ,  Aiichiro Inoue

IPC分类号： G06F9/38 ,  G06F9/49

CPC分类号： G06F9/3806 ,  G06F9/3861

摘要： In an information processing apparatus, an instruction read inhibit bit is provided for branch instruction address and target instruction address registered in pair in the branch history. When the reading of a target instruction predicted from the pair of addresses is inhibited, the instruction read inhibit bit is set to an ON state. When execution of the predicted target instruction is canceled due to the difference between the predicted target instruction and an actual target instruction and the actual target instruction is read again, an instruction read inhibit bit setting section sets the instruction read inhibit bit of the pair of addresses in the branch history to the ON state. Accordingly, even when the information processing apparatus is of a pipeline processing type and the address of the target instruction is changed every time the identical branch instruction appears, it becomes possible to execute the branch instruction without wasting time and to effectively utilize the branch history, thereby increasing the processing speed of the branch instruction, i.e., improving the information processing performance.

摘要翻译： 在信息处理装置中，为分支历史中成对注册的分支指令地址和目标指令地址提供指令读禁止位。 当禁止从该对地址预测的目标指令的读取时，将指令读禁止位设定为ON状态。 当预测目标指令的执行由于预测目标指令与实际目标指令之间的差异而被取消并且再次读取实际目标指令时，指令读取禁止位设置部分设置该对地址的指令读禁止位 在分支历史上到ON状态。 因此，即使当信息处理装置是流水线处理类型，并且每当相同分支指令出现时改变目标指令的地址时，也可以执行分支指令而不浪费时间并有效地利用分支历史， 从而提高分支指令的处理速度，即提高信息处理性能。

公开(公告)号：US06865736B2

公开(公告)日：2005-03-08

申请号：US09784070

申请日：2001-02-16

申请人： Per Anders Holmberg ,  Peter Norrman ,  Leif Karl Johansson ,  Terje Egeland

发明人： Per Anders Holmberg ,  Peter Norrman ,  Leif Karl Johansson ,  Terje Egeland

IPC分类号： G06F11/34 ,  G06F12/08 ,  G06F9/49

CPC分类号： G06F9/5016 ,  G06F11/3409 ,  G06F12/0802 ,  G06F2201/88 ,  G06F2201/885

摘要： The present invention discloses a processor system comprising a processor (31) and at least a first memory (32) and a second memory (34, 36, 37). The first memory (32) is normally faster than the second one, and means for memory allocation (38, 41, 48) perform the periodically static allocation of data into the first memory (32). The means for memory allocation (38, 41, 48) are run-time updateable by software. An execution profiling section (39) is provided for continuously or intermittently providing execution data used for updating the means for memory allocation (38, 41, 48). According to the invention, the memory allocation is performed on a variable or record (49, 50) level. The means for memory allocation preferably use linking tables (41, 48) supporting dynamic software changes. The first memory (32) is preferably an SRAM, connected to the processor by a dedicated bus (33).

摘要翻译： 本发明公开了一种包括处理器（31）和至少第一存储器（32）和第二存储器（34,36,37）的处理器系统。 第一存储器（32）通常比第二存储器（32）快，并且用于存储器分配（38,41,48）的装置执行数据到第一存储器（32）的周期性静态分配。 内存分配（38,41,48）的运行时间可由软件更新。 提供执行分析部分（39），用于连续地或间歇地提供用于更新用于存储器分配的装置（38,41,48）的执行数据。 根据本发明，对变量或记录（49,50）进行存储器分配。 用于存储器分配的装置优选地使用支持动态软件改变的链接表（41,48）。 第一存储器（32）优选地是通过专用总线（33）连接到处理器的SRAM。