公开(公告)号：US06491752B1

公开(公告)日：2002-12-10

申请号：US09354994

申请日：1999-07-16

申请人： Fritz G. Kirscht ,  Peter D. Wildes ,  Volker R. Todt ,  Nobuo Fukuto ,  Boris A. Snegirev ,  Seung-Bae Kim

发明人： Fritz G. Kirscht ,  Peter D. Wildes ,  Volker R. Todt ,  Nobuo Fukuto ,  Boris A. Snegirev ,  Seung-Bae Kim

IPC分类号： H01L21228

CPC分类号： C30B29/06 ,  C30B15/04

摘要： An enhanced n+ silicon material for epitaxial substrates and a method for producing it are described. The enhanced material leads to improved gettering characteristics of n/n+ epitaxial wafers based on these substrates. The method for preparing such n+ silicon material includes applying a co-doping of carbon to the usual n dopant in the silicon melt, before growing respective CZ crystals. This improves yield of enhanced n+ silicon material in crystal growing and ultimately leads to device yield stabilization or improvement when such n/n+ epitaxial wafers are applied in device manufacturing.

摘要翻译： 描述了用于外延衬底的增强的n +硅材料及其制造方法。 增强的材料导致基于这些衬底的n / n +外延晶片的改善的吸杂特性。 制备这种n +硅材料的方法包括在生长各自的CZ晶体之前，将碳共掺杂到硅熔体中的通常的n掺杂剂中。 这提高了晶体生长中增强的n +硅材料的产率，并且当这种n / n +外延晶片应用于器件制造时，最终导致器件产量稳定或改进。

公开(公告)号：US06646476B2

公开(公告)日：2003-11-11

申请号：US10145033

申请日：2002-05-15

申请人： Shou Nagao ,  Munehiro Azami ,  Yoshifumi Tanada

发明人： Shou Nagao ,  Munehiro Azami ,  Yoshifumi Tanada

IPC分类号： H01L21228

摘要： A circuit is provided which is constituted by TFTs of one conductivity type, and which is capable of outputting signals of a normal amplitude. When an input clock signal CK1 becomes a high level, each of TFTs (101, 103) is turned on to settle at a low level the potential at a signal output section (Out). A pulse is then input to a signal input section (In) and becomes high level. The gate potential of TFT (102) is increased to (VDD−V thN) and the gate is floated. TFT (102) is thus turned on. Then CK1 becomes low level and each of TFTs (101, 103) is turned off. Simultaneously, CK3 becomes high level and the potential at the signal output section is increased. Simultaneously, the potential at the gate of TFT (102) is increased to a level equal to or higher than (VDD+V thN) by the function of capacitor (104), so that the high level appearing at the signal output section (Out) becomes equal to VDD. When SP becomes low level; CK3 becomes low level; and CK1 becomes high level, the potential at the signal output section (Out) becomes low level again.