公开(公告)号：US06380029B1

公开(公告)日：2002-04-30

申请号：US09205899

申请日：1998-12-04

申请人： Kent Kuohua Chang ,  Kenneth Wo-Wai Au ,  John Jianshi Wang

发明人： Kent Kuohua Chang ,  Kenneth Wo-Wai Au ,  John Jianshi Wang

IPC分类号： H01L21330

CPC分类号： H01L29/42324 ,  H01L21/28273

摘要： In one embodiment, the present invention relates to a method of forming a flash memory cell, involving the steps of forming a tunnel oxide on a substrate; forming a first polysilicon layer over the tunnel oxide; forming an insulating layer over the first polysilicon layer, the insulating layer comprising a first oxide layer over the first polysilicon layer, a nitride layer over the first oxide layer, and a second oxide layer over the nitride layer; forming a second polysilicon layer over the insulating layer; forming a tungsten silicide layer over the second polysilicon layer by chemical vapor deposition using WF6 and SiH2Cl2; etching at least the first polysilicon layer, the second polysilicon layer, the insulating layer, and the tungsten silicide layer thereby defining at least one stacked gate structure; and forming a source region and a drain region in the substrate, thereby forming at least one memory cell.

摘要翻译： 在一个实施例中，本发明涉及一种形成闪速存储器单元的方法，包括在衬底上形成隧道氧化物的步骤; 在隧道氧化物上形成第一多晶硅层; 在所述第一多晶硅层上形成绝缘层，所述绝缘层包括所述第一多晶硅层上的第一氧化物层，所述第一氧化物层上的氮化物层和所述氮化物层上的第二氧化物层; 在所述绝缘层上形成第二多晶硅层; 通过使用WF 6和SiH 2 Cl 2的化学气相沉积在第二多晶硅层上形成硅化钨层; 至少蚀刻第一多晶硅层，第二多晶硅层，绝缘层和硅化钨层，从而限定至少一个堆叠栅极结构; 以及在衬底中形成源区和漏区，由此形成至少一个存储单元。

公开(公告)号：US06362065B1

公开(公告)日：2002-03-26

申请号：US09794709

申请日：2001-02-26

申请人： Leland S. Swanson ,  Gregory E. Howard

发明人： Leland S. Swanson ,  Gregory E. Howard

IPC分类号： H01L21330

CPC分类号： H01L29/66242 ,  H01L29/0817 ,  H01L29/1608 ,  H01L29/7375 ,  H01L29/7378 ,  H03K19/00315

摘要： The present invention relates to a method of forming a bipolar transistor or a heterojunction bipolar transistor. The method comprises forming a collector region associated with a semiconductor substrate, and forming a base region base region over at least a portion of the collector region. The method further comprises forming a diffusion blocking layer over the base region, and forming an emitter polysilicon region over the diffusion blocking layer. The diffusion blocking layer reduces an amount of diffusion from the emitter polysilicon region into the base region, thereby allowing improved process control and emitter/base doping profile, leading to improved transistor performance. In addition, the present invention relates to a heterojunction bipolar transistor, and comprises a collector region, and a graded profile SiGe base layer overlying the collector region. The transistor further comprises a diffusion blocking layer overlying the graded profile SiGe base layer, and an emitter layer overlying the diffusion blocking layer. The diffusion blocking layer is operable to retard a diffusion of dopants therethrough from the emitter layer to the graded profile SiGe base layer, thereby allowing for a reduction in the thickness of the layer comprising a graded profile SiGe layer and a buffer layer. The thickness reduction allows increased Ge concentration in the base layer and the emitter/base doping profile is improved, each leading to improved transistor performance.

摘要翻译： 本发明涉及形成双极晶体管或异质结双极晶体管的方法。 该方法包括形成与半导体衬底相关联的集电极区域，并且在集电极区域的至少一部分上形成基极区域基极区域。 所述方法还包括在所述基极区上形成扩散阻挡层，以及在所述扩散阻挡层上方形成发射极多晶硅区域。 扩散阻挡层减少了从发射极多晶硅区域到基极区域的扩散量，从而允许改进的工艺控制和发射极/基极掺杂分布，从而提高了晶体管的性能。 此外，本发明涉及异质结双极晶体管，并且包括集电极区域和覆盖在集电极区域上的渐变剖面SiGe基极层。 所述晶体管还包括覆盖所述分级轮廓SiGe基极层的扩散阻挡层和覆盖所述扩散阻挡层的发射极层。 扩散阻挡层可操作以阻止掺杂剂从发射极层到扩散型SiGe基极层的扩散，从而允许降低包含渐变型SiGe层和缓冲层的层的厚度。 厚度减小允许增加基极层中的Ge浓度，改善发射极/基极掺杂分布，从而提高晶体管性能。