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公开(公告)号:US06822314B2
公开(公告)日:2004-11-23
申请号:US10171349
申请日:2002-06-12
申请人: James D. Beasom
发明人: James D. Beasom
IPC分类号: H01L2782
CPC分类号: H01L29/6625 , H01L29/1004 , H01L29/1008 , H01L29/167 , H01L29/66272 , H01L29/7322 , H01L29/735
摘要: An improved base for a NPN bipolar transistor. The base region is formed with Boron and Indium dopants for improved beta early voltage product and reduced base resistance.
摘要翻译: 改进的NPN双极晶体管基极。 碱性区域由硼和铟掺杂物形成,用于改进β早期电压产物和降低的碱电阻。
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公开(公告)号:US06388307B1
公开(公告)日:2002-05-14
申请号:US09376352
申请日:1999-08-18
申请人: Masao Kondo , Katsuya Oda , Katsuyoshi Washio
发明人: Masao Kondo , Katsuya Oda , Katsuyoshi Washio
IPC分类号: H01L2782
CPC分类号: H01L31/1105
摘要: A bipolar transistor using a B-doped Si and Ge alloy for a base in which a Ge content in an emitter-base depletion region and in a base-collector depletion region is greater than a Ge content in a base layer. Diffusion of B from the base layer can be suppressed by making the Ge content in the emitter-base depletion region and in a base-collector depletion region on both sides of the base layer greater than the Ge content in the base layer since the diffusion coefficient of B in the SiGe layer is lowered as the Ge contents increases.
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公开(公告)号:US06653715B2
公开(公告)日:2003-11-25
申请号:US10237674
申请日:2002-09-10
申请人: Masao Kondo , Katsuya Oda , Katsuyoshi Washio
发明人: Masao Kondo , Katsuya Oda , Katsuyoshi Washio
IPC分类号: H01L2782
CPC分类号: H01L31/1105
摘要: A bipolar transistor using a B-doped Si and Ge alloy for a base in which a Ge content in an emitter-base depletion region and in a base-collector depletion region is greater than a Ge content in a base layer. Diffusion of B from the base layer can be suppressed by making the Ge content in the emitter-base depletion region and in a base-collector depletion region on both sides of the base layer greater than the Ge content in the base layer since the diffusion coefficient of B in the SiGe layer is lowered as the Ge contents increases.
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公开(公告)号:US06545328B1
公开(公告)日:2003-04-08
申请号:US09548633
申请日:2000-04-12
申请人: Narihiro Morosawa , Hiroshi Iwata
发明人: Narihiro Morosawa , Hiroshi Iwata
IPC分类号: H01L2782
CPC分类号: H01L29/41783 , H01L21/28035 , H01L21/28052 , H01L21/32105 , H01L21/32155 , H01L21/823814 , H01L21/823828 , H01L29/4916 , H01L29/665 , H01L29/66545
摘要: A semiconductor device includes an insulating gate field effect transistor including a gate electrode, wherein the gate electrode includes a polycrystalline semiconductor film having a crystal defect density of about 1×1018 cm−3 or less. In certain embodiments, the polycrystalline semiconductor film may be oxidation thermally annealed by subjecting the polycrystalline semiconductor film to thermal treatment in an oxidation atmosphere to carry out oxidization of the polycrystalline semiconductor film and activation of impurities simultaneously.
摘要翻译: 半导体器件包括具有栅电极的绝缘栅场效应晶体管,其中栅电极包括晶体缺陷密度约为1×1018cm-3或更小的多晶半导体膜。 在某些实施方案中,多晶半导体膜可以通过在多晶半导体膜中在氧化气氛中进行热处理来进行氧化热退火,以进行多晶半导体膜的氧化和同时活化杂质。
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公开(公告)号:US06483170B2
公开(公告)日:2002-11-19
申请号:US09975519
申请日:2001-10-10
申请人: Ted Johansson
发明人: Ted Johansson
IPC分类号: H01L2782
CPC分类号: H01L23/647 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要: A method for manufacturing a silicon bipolar power high frequency transistor device is disclosed. A transistor device according to the present method is also disclosed. The transistor device assures conditions for maintaining a proper BVCER to avoid collector emitter breakdown during operation. According to the method an integrated resistor is arranged along at least one side of a silicon bipolar transistor on a semiconductor die which constitutes a substrate for the silicon bipolar transistor. The integrated resistor is connected between the base and emitter terminals of the silicon bipolar transistor. The added integrated resistor is a diffused p+ resistor on said semiconductor die or a polysilicon or NiCr resistor placed on top of the isolation layers. In an interdigitated transistor structure provided with integrated emitter ballast resistors the added- resistor or resistors (20) will be manufactured in a step simultaneously as producing the ballast resistors.
摘要翻译: 公开了一种制造硅双极型高功率高频晶体管器件的方法。 还公开了根据本方法的晶体管器件。 晶体管器件确保维持适当的BVCER的条件,以避免在操作期间的集电极发射极击穿。 根据该方法,在构成硅双极晶体管的衬底的半导体管芯上沿着硅双极晶体管的至少一侧布置集成电阻器。 集成电阻器连接在硅双极晶体管的基极和发射极端子之间。 添加的集成电阻器是在所述半导体管芯上的扩散的p +电阻器或放置在隔离层顶部上的多晶硅或NiCr电阻器。 在配有集成发射极镇流电阻的交错晶体管结构中,加法电阻或电阻(20)将同时制作制造镇流电阻。
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