公开(公告)号：US07410860B2

公开(公告)日：2008-08-12

申请号：US11238344

申请日：2005-09-29

申请人： James D. Beasom

发明人： James D. Beasom

IPC分类号： H01L21/8234

CPC分类号： H01L29/0847 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/402 ,  H01L29/66659 ,  H01L29/735 ,  H01L29/7835 ,  H01L29/8611 ,  H01L2924/0002 ,  H03K17/941 ,  H01L2924/00

摘要： Apparatus and Methods for the self-alignment of separated regions in a lateral MOSFET of an integrate circuit. In one embodiment, a method comprising, forming a relatively thin dielectric layer on a surface of a substrate. Forming a first region of relatively thick material having a predetermined lateral length on the surface of the substrate adjacent the relatively thin dielectric layer. Implanting dopants to form a top gate using a first edge of the first region as a mask to define a first edge of the top gate. Implanting dopants to form a drain contact using a second edge of the first region as a mask to define a first edge of the drain contact, wherein the distance between the top gate and drain contact is defined by the lateral length of the first region.

摘要翻译： 用于集成电路的横向MOSFET中分离区域的自对准的装置和方法。 在一个实施例中，一种方法包括：在衬底的表面上形成相对薄的电介质层。 在相邻较薄的电介质层的基板的表面上形成具有预定横向长度的较厚材料的第一区域。 使用第一区域的第一边缘作为掩模将植入掺杂剂形成顶部栅极以限定顶部栅极的第一边缘。 使用第一区域的第二边缘作为掩模来植入掺杂剂以形成漏极接触，以限定漏极接触的第一边缘，其中顶部栅极和漏极接触之间的距离由第一区域的横向长度限定。

公开(公告)号：US06979885B2

公开(公告)日：2005-12-27

申请号：US10360374

申请日：2003-02-06

申请人： James D. Beasom

发明人： James D. Beasom

IPC分类号： H01L21/225 ,  H01L21/266 ,  H01L21/336 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/732 ,  H01L27/082 ,  H01L27/102 ,  H01L29/70 ,  H01L29/76 ,  H01L29/94

CPC分类号： H01L29/6659 ,  H01L21/2253 ,  H01L21/266 ,  H01L29/0692 ,  H01L29/0821 ,  H01L29/1079 ,  H01L29/7322

摘要： In a semiconductor substrate with a top surface, a PN junction between a first region of one conductivity type formed by masked diffusion into a semiconductor from the surface and a second region of opposite conductivity type formed into a first portion of the first region from the surface. The improvement comprising edges of the first region being spaced from associated edges of the second region such that the doping concentration of the first region at the surface intersection of corners of the junction between the first and second regions is lower than it is at some other location in the first region.

摘要翻译： 在具有顶表面的半导体衬底中，通过从表面掩模扩散到半导体中形成的一种导电类型的第一区域和相反导电类型的第二区域之间的PN结从该表面形成第一区域的第一部分 。 改进包括第一区域的边缘与第二区域的相关边缘间隔开，使得在第一和第二区域之间的结点的角部的表面交叉处的第一区域的掺杂浓度低于在另一个位置 在第一个地区。

公开(公告)号：US06894349B2

公开(公告)日：2005-05-17

申请号：US10104342

申请日：2002-03-22

申请人： James D. Beasom

发明人： James D. Beasom

IPC分类号： H01L21/336 ,  H01L29/06 ,  H01L29/08 ,  H01L29/78 ,  H01L29/76

CPC分类号： H01L29/66659 ,  H01L29/0634 ,  H01L29/7816 ,  H01L29/7835

摘要： A high voltage lateral semiconductor device for integrated circuits with improved breakdown voltage. The semiconductor device comprising a semiconductor body, an extended drain region formed in the semiconductor body, source and drain pockets, a top gate forming a pn junction with the extended drain region, an insulating layer on a surface of the semiconductor body and a gate formed on the insulating layer. In addition, a higher-doped pocket of semiconductor material is formed within the top gate region that has a higher integrated doping than the rest of the top gate region. This higher-doped pocket of semiconductor material does not totally deplete during device operation. Moreover, the gate controls, by field-effect, a flow of current through a channel formed laterally between the source pocket and a nearest point of the extended drain region.

公开(公告)号：US06867495B2

公开(公告)日：2005-03-15

申请号：US09961613

申请日：2001-09-24

申请人： Joseph A. Czagas ,  Dustin A. Woodbury ,  James D. Beasom

发明人： Joseph A. Czagas ,  Dustin A. Woodbury ,  James D. Beasom

IPC分类号： H01L21/22 ,  H01L21/02 ,  H01L21/18 ,  H01L21/20 ,  H01L21/225 ,  H01L21/265 ,  H01L21/336 ,  H01L21/74 ,  H01L21/762 ,  H01L27/12 ,  H01L29/06 ,  H01L29/10 ,  H01L29/78 ,  H01L23/48 ,  H01L27/01 ,  H01L21/76

CPC分类号： H01L21/2253 ,  H01L21/187 ,  H01L21/2007 ,  H01L21/2255 ,  H01L21/2256 ,  H01L21/26513 ,  H01L21/74 ,  H01L21/76251 ,  H01L29/0615 ,  H01L29/10 ,  H01L29/1079 ,  H01L29/1083 ,  Y10S438/933

摘要： Integrated circuits, semiconductor devices and methods for making the same are described. Each embodiment shows a diffused, doped backside layer in a device wafer that is oxide bonded to a handle wafer. The diffused layer may originate in the device handle, in the handle wafer, in the bond oxide or in an additional semiconductor layer of polysilicon or epitaxial silicon. The methods use a thermal bond oxide or a combination of a thermal and deposited oxide.

公开(公告)号：US06552392B2

公开(公告)日：2003-04-22

申请号：US09899332

申请日：2001-07-03

申请人： James D. Beasom

发明人： James D. Beasom

IPC分类号： H01L2976

CPC分类号： H01L29/0878 ,  H01L29/0615 ,  H01L29/0847 ,  H01L29/0882 ,  H01L29/1087 ,  H01L29/7835

摘要： An integrated circuit having a high voltage lateral MOS with reduced ON resistance. In one embodiment, the integrated circuit includes a high voltage lateral MOS with an island formed in a substrate, a source, a gate and a first and second drain extension. The island is doped with a low density first conductivity type. The source and drain contact are both doped with a high density second conductivity type. The first drain extension is of the second conductivity type and extends laterally from under the gate past the drain contact. The second drain extension is of the second conductivity type and extends laterally from under the gate toward the source. A portion of the second drain extension overlaps the first drain extension under the gate to form a region of increased doping of the second conductivity type.

摘要翻译： 具有降低的导通电阻的具有高电压横向MOS的集成电路。 在一个实施例中，集成电路包括高压横向MOS，其中形成在衬底中的岛，源极，栅极以及第一和第二漏极延伸。 该岛掺杂有低密度第一导电类型。 源极和漏极接触均掺杂有高密度第二导电类型。 第一漏极延伸部是第二导电类型，并且从栅极下方横向延伸穿过漏极接触。 第二漏极延伸部是第二导电类型，并且从栅极下方向源极侧向延伸。 第二漏极延伸部分与栅极之下的第一漏极延伸部分重叠以形成第二导电类型的掺杂增加的区域。

公开(公告)号：US5929502A

公开(公告)日：1999-07-27

申请号：US868813

申请日：1997-06-04

申请人： James D. Beasom

发明人： James D. Beasom

IPC分类号： H01L29/861 ,  H01L29/866 ,  H03K5/24 ,  H03L5/00

CPC分类号： H01L29/861 ,  H01L29/866 ,  H03K5/2418

摘要： A punch-through diode includes a first and second gate forming first and second junctions respectively with and spaced from each other by a first region. The junctions may be PN junction or Schottky barrier junctions with the first region. The diode may be the top gate-channel-bottom gate junctions of an FET or the collector-base-emitter junctions of a bipolar transistor. In either case, the channel or the base is depleted and currents flow between the top and bottom gate or the emitter and collector respectively. The punch-through diode is used as a voltage reference element and can be structured for Kelvin connection.

摘要翻译： 穿通二极管包括第一和第二栅极，第一和第二栅极分别由第一区域彼此间隔开并形成第一和第二结。 结可以是与第一区域的PN结或肖特基势垒结。 二极管可以是FET的顶栅极通道 - 底栅极结或双极晶体管的集电极 - 基极 - 发射极结。 在任一种情况下，通道或基极都耗尽，并且电流分别在顶部栅极或底部栅极或发射极和集电极之间流动。 穿通二极管用作电压参考元件，可以用于开尔文连接。

公开(公告)号：US5776814A

公开(公告)日：1998-07-07

申请号：US775360

申请日：1997-01-03

申请人： James D. Beasom

发明人： James D. Beasom

IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L21/8228 ,  H01L27/082 ,  H01L29/732

CPC分类号： H01L27/0826 ,  H01L21/8228 ,  H01L27/082

摘要： A reduced mask set, implant complexity process for manufacturing a (high frequency application) complementary bipolar transistor structure uses the fast lateral diffusion characteristic of a layer of material, that is at least an order of magnitude higher for emitter dopants than in single crystal semiconductor material. Separate base and emitter poly layers are formed undoped. Then, the emitter poly of one device and the edges of the base poly of the other device are exposed through a dopant mask and simultaneously doped. The emitter dopant goes directly into the surface of the emitter poly where it lies over and is in contact with the base. The base contact dopant goes into the edges of the base poly, including the layer of material having the high diffusion coefficient, rapidly diffuses laterally throughout that layer, and then diffuses down into the collector material (e.g. island) surface, to form the extrinsic base. A second mask is patterned to expose the emitter of the second device and the edges of the base poly of the first device. Each device is then doped with the second type impurity through the second mask. The use of the high diffusion coefficient layer in the base contact enables the base dopant to spread laterally from the edge contact to the region where the base poly is in contact with the collector, with the same diffusion cycle that is used for the emitter.

摘要翻译： 减少的掩模组，用于制造（高频应用）互补双极晶体管结构的植入复杂度过程使用材料层的快速横向扩散特性，其比发射体掺杂物比单晶半导体材料高至少一个数量级 。 单独的基极和发射极多晶层形成为未掺杂的。 然后，一个器件的发射极多晶硅和另一个器件的基极聚合物的边缘通过掺杂剂掩模曝光并同时掺杂。 发射极掺杂剂直接进入发射极聚合物的表面，其位于其上并与基底接触。 基极接触掺杂剂进入基极聚合物的边缘，包括具有高扩散系数的材料层，在该层上横向扩散，然后扩散到收集器材料（例如岛）表面中，以形成外部基极 。 图案化第二掩模以暴露第二器件的发射极和第一器件的基极poly的边缘。 然后每个器件通过第二掩模掺杂第二类型杂质。 在基极接触中使用高扩散系数层使得基底掺杂剂从边缘接触侧向扩散到与聚集体接触的区域，具有与用于发射极的相同的扩散循环。

公开(公告)号：US5622890A

公开(公告)日：1997-04-22

申请号：US279027

申请日：1994-07-22

申请人： James D. Beasom ,  Dustin A. Woodbury

发明人： James D. Beasom ,  Dustin A. Woodbury

IPC分类号： H01L21/768 ,  H01L23/485 ,  H01L21/302

CPC分类号： H01L21/768 ,  H01L23/485 ,  H01L2924/0002 ,  Y10S438/975

摘要： A contact region for a trench in a semiconductor device and a method for electrically contacting the conductive material in a trench that is too narrow for conventional electrical contacts may include a contact region in which the trench is divided into two or more trench sections, each section having the same narrow width as the undivided trench. The two or more trench sections are separated by one or more islands that are isolated from the semiconductor device. An aperture through the material above the contact region provides access for electrically contacting the conductive material in the trench sections.

摘要翻译： 用于半导体器件中的沟槽的接触区域和用于使沟槽中的导电材料电接触的方法对于传统的电触点来说太窄可包括其中沟槽被划分成两个或多个沟槽部分的接触区域， 具有与未分割沟槽相同的窄宽度。 两个或多个沟槽部分由与半导体器件隔离的一个或多个岛分开。 穿过接触区域上方的材料的孔提供用于电接触沟槽部分中的导电材料的通路。

公开(公告)号：US5614422A

公开(公告)日：1997-03-25

申请号：US405660

申请日：1995-03-17

申请人： James D. Beasom

发明人： James D. Beasom

IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L21/8228 ,  H01L27/082 ,  H01L29/732 ,  H01L21/265

CPC分类号： H01L27/0826 ,  H01L21/8228 ,  H01L27/082

摘要： A reduced mask set, implant complexity process for manufacturing a (high frequency application) complementary bipolar transistor structure uses the fast lateral diffusion characteristic of a layer of material, that is at least an order of magnitude higher for emitter dopants than in single crystal semiconductor material. Separate base and emitter poly layers are formed undoped. Then, the emitter poly of one device and the edges of the base poly of the other device are exposed through a dopant mask and simultaneously doped. The emitter dopant goes directly into the surface of the emitter poly where it lies over and is in contact with the base. The base contact dopant goes into the edges of the base poly, including the layer of material having the high diffusion coefficient, rapidly diffuses laterally throughout that layer, and then diffuses down into the collector material (e.g. island) surface, to form the extrinsic base. A second mask is patterned to expose the emitter of the second device and the edges of the base poly of the first device. Each device is then doped with the second type impurity through the second mask. The use of the high diffusion coefficient layer in the base contact enables the base dopant to spread laterally from the edge contact to the region where the base poly is in contact with the collector, with the same diffusion cycle that is used for the emitter.

摘要翻译： 减少的掩模组，用于制造（高频应用）互补双极晶体管结构的植入复杂度过程使用材料层的快速横向扩散特性，其比发射体掺杂物比单晶半导体材料高至少一个数量级 。 单独的基极和发射极多晶层形成为未掺杂的。 然后，一个器件的发射极多晶硅和另一个器件的基极聚合物的边缘通过掺杂剂掩模曝光并同时掺杂。 发射极掺杂剂直接进入发射极聚合物的表面，其位于其上并与基底接触。 基极接触掺杂剂进入基极聚合物的边缘，包括具有高扩散系数的材料层，在该层上横向扩散，然后扩散到收集器材料（例如岛）表面中，以形成外部基极 。 图案化第二掩模以暴露第二器件的发射极和第一器件的基极poly的边缘。 然后每个器件通过第二掩模掺杂第二类型杂质。 在基极接触中使用高扩散系数层使得基底掺杂剂从边缘接触侧向扩散到与聚集体接触的区域，具有与用于发射极的相同的扩散循环。

公开(公告)号：US5602054A

公开(公告)日：1997-02-11

申请号：US309573

申请日：1994-09-21

申请人： James D. Beasom

发明人： James D. Beasom

IPC分类号： H01L21/762 ,  H01L27/092 ,  H01L21/225

CPC分类号： H01L27/0921 ,  H01L21/76297 ,  Y10S148/135 ,  Y10S148/168

摘要： A dielectrically isolated island architecture in which the island is contoured inwardly to form one or more projections that penetrate a well separating two regions in the island to assure that the two regions will be electrically isolated without additional processing steps.

摘要翻译： 一种介电隔离的岛屿结构，其中岛向内成形以形成一个或多个突出物，其穿透分离岛中的两个区域的阱，以确保两个区域将被电隔离而无需额外的处理步骤。