公开(公告)号：US06249031B1

公开(公告)日：2001-06-19

申请号：US09534551

申请日：2000-03-27

申请人： Purakh Raj Verma ,  Joe Jin Kuek

发明人： Purakh Raj Verma ,  Joe Jin Kuek

IPC分类号： H01L29735

CPC分类号： H01L29/6625 ,  H01L21/8249

摘要： A method and lateral bipolar transistor structure are achieved, with high current gain, compatible with CMOS processing to form BiCMOS circuits. Making a lateral PNP bipolar involves forming an N− well in a P− doped silicon substrate. A patterned Si3N4 layer is used as an oxidation barrier mask to form field oxide isolation around device areas by the LOCOS method. A polysilicon layer over device areas is patterned to leave portions over the intrinsic base areas of the L-PNP bipolar an implant block-out mask. A buried N− base region is implanted in the substrate under the emitter region. A photoresist mask and the patterned polysilicon layer are used to implant the P++ doped emitter and collector for the L-PNP. The emitter junction depth xj intersects the highly doped N+ buried base region. This N+ doped base under the emitter reduces the current gain of the unwanted (parasitic) vertical PNP portion of the L-PNP bipolar to reduce the current gain of the V-PNP. The built-in potential Vbi of the emitter-base junction also increases further the current gain of the V-PNP thereby increasing the gain of the L-PNP bipolar transistor. By reversing the polarity of the dopants, L-NPN components can also be made. Also by implanting a tetravalent impurity such as Ge, Si, or C, the current gain of the L-PNP can be further improved.

摘要翻译： 实现了一种方法和横向双极晶体管结构，具有高电流增益，与CMOS处理兼容以形成BiCMOS电路。 制造横向PNP双极性涉及在P-掺杂硅衬底中形成N-阱。 使用图案化的Si 3 N 4层作为氧化屏蔽掩模，通过LOCOS方法在器件区域周围形成场氧化物隔离。 在器件区域上的多晶硅层被图案化以在L-PNP双极的固有基极区域上留下部分注入阻挡掩模。 掩埋的N基区被注入到发射极区下的衬底中。 光致抗蚀剂掩模和图案化的多晶硅层用于注入用于L-PNP的P ++掺杂的发射极和集电极。 发射极结深度xj与高掺杂的N +掩埋基极区域相交。 发射极下的这个N +掺杂的基极减小了L-PNP双极的不需要的（寄生）垂直PNP部分的电流增益，以减小V-PNP的电流增益。 发射极 - 基极结的内置电位Vbi也进一步增加了V-PNP的电流增益，从而增加了L-PNP双极晶体管的增益。 通过反转掺杂剂的极性，也可以制造L-NPN组分。 通过注入诸如Ge，Si或C的四价杂质，可以进一步提高L-PNP的电流增益。

公开(公告)号：US06657279B1

公开(公告)日：2003-12-02

申请号：US09637956

申请日：2000-08-11

申请人： Angelo Pinto ,  Carlo Alemanni

发明人： Angelo Pinto ,  Carlo Alemanni

IPC分类号： H01L29735

CPC分类号： H01L29/6625 ,  H01L21/8228 ,  H01L27/082 ,  H01L29/735

摘要： The invention relates to a process for making a lateral PNP bipolar electronic device integrated monolithically on a semiconductor substrate together with other bipolar devices of the NPN type, said device being incorporated to an electrically insulated multilayer structure. The device includes a semiconductor substrate doped with impurities of the P type; a first buried layer doped with impurities of the N type to form a base region; and a second layer, overlying the first and having conductivity of the N type, to form an active area with opposite collector and emitter regions being formed in said active area and separated by a base channel region. The width of the base channel region is defined essentially by a contact opening formed above an oxide layer deposited over the base channel region. Advantageously, the contact opening is formed by shifting an emitter mask.

摘要翻译： 本发明涉及一种用于制造横向PNP双极电子器件的方法，其与NPN型的其它双极器件一体地集成在半导体衬底上，所述器件被并入到电绝缘的多层结构中。 该器件包括掺杂有P型杂质的半导体衬底; 掺杂有N型杂质的第一掩埋层以形成基极区; 以及覆盖第一层并具有N型导电性的第二层，以形成有源区域，其中相反的集电极和发射极区域形成在所述有源区域中并由基极沟道区域分隔开。 基本通道区域的宽度基本上由形成在沉积在基底通道区域上的氧化物层上方的接触开口限定。 有利地，通过移动发射器掩模来形成接触开口。

公开(公告)号：US06326674B1

公开(公告)日：2001-12-04

申请号：US09451623

申请日：1999-11-30

申请人： Jong-Hwan Kim ,  Tae-Hoon Kwon ,  Cheol-Joong Kim ,  Suk-Kyun Lee

发明人： Jong-Hwan Kim ,  Tae-Hoon Kwon ,  Cheol-Joong Kim ,  Suk-Kyun Lee

IPC分类号： H01L29735

CPC分类号： H01L21/8226 ,  H01L21/8224 ,  H01L21/8228 ,  H01L21/82285 ,  H01L27/0233 ,  H01L27/0647 ,  H01L27/0826

摘要： A complementary bipolar transistor having a lateral npn bipolar transistor, a vertical and a lateral pnp bipolar transistor, an integrated injection logic, a diffusion capacitor, a polysilicon capacitor and polysilicon resistors are disclosed. The lateral pnp bipolar transistor has an emitter region and a collector region which includes high-density regions and low-density regions, and the emitter region is formed in an n type tub region. In the integrated injection logic circuit, collector regions are surrounded by a high-density p type region, and low-density p type regions are formed under the collector regions. The diffusion capacitor and the polysilicon capacitor are formed in one substrate. The diffusion regions except the regions formed by diffusing the impurities in the polysilicon resistors into the epitaxial layer are formed before forming the polysilicon resistors, and polysilicon electrodes are formed along with the polysilicon resistors.

摘要翻译： 公开了具有横向npn双极晶体管，垂直和横向pnp双极晶体管，集成注入逻辑，扩散电容器，多晶硅电容器和多晶硅电阻器的互补双极晶体管。 横向pnp双极晶体管具有包括高密度区域和低密度区域的发射极区域和集电极区域，并且发射极区域形成在n型槽区域中。 在集成注入逻辑电路中，集电极区域被高密度p型区域包围，在集电极区域形成低密度p型区域。 扩散电容器和多晶硅电容器形成在一个衬底中。 在形成多晶硅电阻器之前形成除了将多晶硅电阻器中的杂质扩散到外延层中形成的区域之外的扩散区域，并且多晶硅电极与多晶硅电阻器一起形成。