公开(公告)号：US06249031B1

公开(公告)日：2001-06-19

申请号：US09534551

申请日：2000-03-27

申请人： Purakh Raj Verma ,  Joe Jin Kuek

发明人： Purakh Raj Verma ,  Joe Jin Kuek

IPC分类号： H01L29735

CPC分类号： H01L29/6625 ,  H01L21/8249

摘要： A method and lateral bipolar transistor structure are achieved, with high current gain, compatible with CMOS processing to form BiCMOS circuits. Making a lateral PNP bipolar involves forming an N− well in a P− doped silicon substrate. A patterned Si3N4 layer is used as an oxidation barrier mask to form field oxide isolation around device areas by the LOCOS method. A polysilicon layer over device areas is patterned to leave portions over the intrinsic base areas of the L-PNP bipolar an implant block-out mask. A buried N− base region is implanted in the substrate under the emitter region. A photoresist mask and the patterned polysilicon layer are used to implant the P++ doped emitter and collector for the L-PNP. The emitter junction depth xj intersects the highly doped N+ buried base region. This N+ doped base under the emitter reduces the current gain of the unwanted (parasitic) vertical PNP portion of the L-PNP bipolar to reduce the current gain of the V-PNP. The built-in potential Vbi of the emitter-base junction also increases further the current gain of the V-PNP thereby increasing the gain of the L-PNP bipolar transistor. By reversing the polarity of the dopants, L-NPN components can also be made. Also by implanting a tetravalent impurity such as Ge, Si, or C, the current gain of the L-PNP can be further improved.

摘要翻译： 实现了一种方法和横向双极晶体管结构，具有高电流增益，与CMOS处理兼容以形成BiCMOS电路。 制造横向PNP双极性涉及在P-掺杂硅衬底中形成N-阱。 使用图案化的Si 3 N 4层作为氧化屏蔽掩模，通过LOCOS方法在器件区域周围形成场氧化物隔离。 在器件区域上的多晶硅层被图案化以在L-PNP双极的固有基极区域上留下部分注入阻挡掩模。 掩埋的N基区被注入到发射极区下的衬底中。 光致抗蚀剂掩模和图案化的多晶硅层用于注入用于L-PNP的P ++掺杂的发射极和集电极。 发射极结深度xj与高掺杂的N +掩埋基极区域相交。 发射极下的这个N +掺杂的基极减小了L-PNP双极的不需要的（寄生）垂直PNP部分的电流增益，以减小V-PNP的电流增益。 发射极 - 基极结的内置电位Vbi也进一步增加了V-PNP的电流增益，从而增加了L-PNP双极晶体管的增益。 通过反转掺杂剂的极性，也可以制造L-NPN组分。 通过注入诸如Ge，Si或C的四价杂质，可以进一步提高L-PNP的电流增益。

公开(公告)号：US6093613A

公开(公告)日：2000-07-25

申请号：US020496

申请日：1998-02-09

申请人： Purakh Raj Verma ,  Joe Jin Kuek

发明人： Purakh Raj Verma ,  Joe Jin Kuek

IPC分类号： H01L21/331 ,  H01L21/8249

CPC分类号： H01L29/6625 ,  H01L21/8249

摘要： A method and lateral bipolar transistor structure are achieved, with high current gain, compatible with CMOS processing to form BiCMOS circuits. Making a lateral PNP bipolar involves forming an N.sup.- well in a P.sup.- doped silicon substrate. A patterned Si.sub.3 N.sub.4 layer is used as an oxidation barrier mask to form field oxide isolation around device areas by the LOCOS method. A polysilicon layer over device areas is patterned to leave portions over the intrinsic base areas of the L-PNP bipolar an implant block-out mask. A buried N.sup.- base region is implanted in the substrate under the emitter region. A photoresist mask and the patterned polysilicon layer are used to implant the P.sup.++ doped emitter and collector for the L-PNP. The emitter junction depth x.sub.j intersects the highly doped N.sup.+ buried base region. This N.sup.+ doped base under the emitter reduces the current gain of the unwanted (parasitic) vertical PNP portion of the L-PNP bipolar to reduce the current gain of the V-PNP. The built-in potential V.sub.bi of the emitter-base junction also increases further the current gain of the V-PNP thereby increasing the gain of the L-PNP bipolar transistor. By reversing the polarity of the dopants, L-NPN components can also be made. Also by implanting a tetravalent impurity such as Ge, Si, or C, the current gain of the L-PNP can be further improved.

摘要翻译： 实现了一种方法和横向双极晶体管结构，具有高电流增益，与CMOS处理兼容以形成BiCMOS电路。 制造横向PNP双极性涉及在P-掺杂硅衬底中形成N-阱。 使用图案化的Si 3 N 4层作为氧化屏蔽掩模，通过LOCOS方法在器件区域周围形成场氧化物隔离。 在器件区域上的多晶硅层被图案化以在L-PNP双极的固有基极区域上留下部分注入阻挡掩模。 掩埋的N基区被注入到发射极区下的衬底中。 光致抗蚀剂掩模和图案化的多晶硅层用于注入用于L-PNP的P ++掺杂的发射极和集电极。 发射极结深度xj与高掺杂的N +掩埋基极区域相交。 发射极下的这个N +掺杂的基极减小了L-PNP双极的不需要的（寄生）垂直PNP部分的电流增益，以减小V-PNP的电流增益。 发射极 - 基极结的内置电位Vbi也进一步增加了V-PNP的电流增益，从而增加了L-PNP双极晶体管的增益。 通过反转掺杂剂的极性，也可以制造L-NPN组分。 通过注入诸如Ge，Si或C的四价杂质，可以进一步提高L-PNP的电流增益。

公开(公告)号：US08802484B1

公开(公告)日：2014-08-12

申请号：US13747009

申请日：2013-01-22

申请人： Purakh Raj Verma ,  Guowei Zhang ,  Kah Wee Ang

发明人： Purakh Raj Verma ,  Guowei Zhang ,  Kah Wee Ang

IPC分类号： H01L21/00 ,  H01L31/102

CPC分类号： H01L21/02532 ,  H01L21/84 ,  H01L27/0617 ,  H01L27/1203 ,  H01L31/028

摘要： A method and device are provided for forming an integrated Ge or Ge/Si photo detector in the CMOS process by non-selective epitaxial growth of the Ge or Ge/Si. Embodiments include forming an N-well in a Si substrate; forming a transistor or resistor in the Si substrate; forming an ILD over the Si substrate and the transistor or resistor; forming a Si-based dielectric layer on the ILD; forming a poly-Si or a-Si layer on the Si-based dielectric layer; forming a trench in the poly-Si or a-Si layer, the Si-based dielectric layer, the ILD, and the N-well; forming Ge or Ge/Si in the trench; and removing the Ge or Ge/Si, the poly-Si or a-Si layer, and the Si-based dielectric layer down to an upper surface of the ILD. Further aspects include forming an in-situ doped Si cap epilayer or an ex-situ doped poly-Si or a-Si cap layer on the Ge or Ge/Si.

摘要翻译： 提供了一种通过Ge或Ge / Si的非选择性外延生长在CMOS工艺中形成集成的Ge或Ge / Si光电检测器的方法和装置。 实施例包括在Si衬底中形成N阱; 在Si衬底中形成晶体管或电阻器; 在Si衬底和晶体管或电阻器上形成ILD; 在ILD上形成Si基电介质层; 在所述Si基电介质层上形成多晶硅或Si-Si层; 在多晶硅或a-Si层中形成沟槽，Si基介电层，ILD和N阱; 在沟槽中形成Ge或Ge / Si; 并且将Ge或Ge / Si，多晶硅或a-Si层以及Si基介电层除去到ILD的上表面。 另外的方面包括在Ge或Ge / Si上形成原位掺杂的Si帽外延层或非原位掺杂的多晶Si或者a-Si覆盖层。

公开(公告)号：US08645876B2

公开(公告)日：2014-02-04

申请号：US13234117

申请日：2011-09-15

申请人： Wye Boon Loh ,  Jeoung Mo Koo ,  Paul Kim Cheong Soh ,  Beng Lye Oh ,  Purakh Raj Verma

发明人： Wye Boon Loh ,  Jeoung Mo Koo ,  Paul Kim Cheong Soh ,  Beng Lye Oh ,  Purakh Raj Verma

IPC分类号： G06F17/50

CPC分类号： G06F17/5081

摘要： There is provided a method comprising receiving data corresponding to a layout design for a plurality of input mask layers and generating a layout design for at least one generated mask layer. The relationship between a first geometric element in a first layout pattern comprising one or more of the generated mask layers and a second geometric element in a second layout pattern is then determined and verified to check if they comply with predetermined rules. If the relationship does not conform with the predetermined rules the design of at least one of the generated mask layers associated with the first or second layout pattern is modified.

摘要翻译： 提供了一种方法，包括接收对应于多个输入掩模层的布局设计的数据，并且生成用于至少一个生成的掩模层的布局设计。 然后确定并验证包括生成的掩模层中的一个或多个的第一布局图案中的第一几何元素与第二布局图案中的第二几何元素之间的关系，以检查它们是否符合预定规则。 如果关系不符合预定规则，则修改与第一或第二布局图案相关联的所生成的掩模层中的至少一个的设计。

公开(公告)号：US08507983B2

公开(公告)日：2013-08-13

申请号：US13550571

申请日：2012-07-16

申请人： Guowei Zhang ,  Purakh Raj Verma

发明人： Guowei Zhang ,  Purakh Raj Verma

IPC分类号： H01L29/76

CPC分类号： H01L29/0847 ,  H01L21/26586 ,  H01L21/823807 ,  H01L27/0922 ,  H01L29/0653 ,  H01L29/1045 ,  H01L29/66659 ,  H01L29/7835

摘要： A device is disclosed. The device includes s substrate prepared with an active device region. The active device region includes a gate. The device also includes a doped channel well disposed in the substrate adjacent to a first edge of the gate. The first edge of the gate overlaps the channel well with a channel edge of the channel well beneath the gate. The first edge of the gate and channel edge defines an effective channel length of the device. The effective channel length is self-aligned to the gate. A doped drift well adjacent to a second edge of the gate is also included.

摘要翻译： 公开了一种设备。 该器件包括用有源器件区域制备的衬底。 有源器件区域包括栅极。 该器件还包括在栅极的第一边缘附近设置在衬底中的掺杂沟道。 栅极的第一边缘与沟道的沟道边缘很好地与沟道的沟道边缘重叠。 栅极和沟道边缘的第一个边缘定义了器件的有效沟道长度。 有效通道长度与栅极自对准。 还包括与栅极的第二边缘相邻的掺杂漂移阱。

公开(公告)号：US08450832B2

公开(公告)日：2013-05-28

申请号：US11696732

申请日：2007-04-05

申请人： Manju Sarkar ,  Purakh Raj Verma

发明人： Manju Sarkar ,  Purakh Raj Verma

IPC分类号： H01L29/93

CPC分类号： H01L27/0808 ,  H01L29/93

摘要： Large tuning range junction varactor includes first and second junction capacitors coupled in parallel between first and second varactor terminals. First and second plates of the capacitors are formed by three alternating doped regions in a substrate. The first and third doped regions are of the same type sandwiching the second doped region of the second type. A first input terminal is coupled to the first and third doped regions and a second terminal is coupled to the second doped region. At the interfaces of the doped regions are first and second depletion regions whose width can be varied by varying the voltage across the terminals from zero to full reverse bias.

摘要翻译： 大型调谐范围结变容二极管包括并联在第一和第二变容二极管端子之间的第一和第二结电容器。 电容器的第一和第二板由衬底中的三个交替掺杂区域形成。 第一和第三掺杂区域具有夹着第二类型的第二掺杂区域的相同类型。 第一输入端子耦合到第一和第三掺杂区域，第二端子耦合到第二掺杂区域。 在掺杂区域的界面处是第一和第二耗尽区域，其宽度可以通过将端子间的电压从零改变为全反向偏压来改变。

公开(公告)号：US08410553B2

公开(公告)日：2013-04-02

申请号：US12964753

申请日：2010-12-10

申请人： Jeoung Mo Koo ,  Purakh Raj Verma ,  Sanford Chu ,  Chunlin Zhu ,  Yisuo Li

发明人： Jeoung Mo Koo ,  Purakh Raj Verma ,  Sanford Chu ,  Chunlin Zhu ,  Yisuo Li

IPC分类号： H01L29/78

CPC分类号： H01L29/0847 ,  H01L29/0653 ,  H01L29/105 ,  H01L29/66568 ,  H01L29/7833

摘要： A high voltage device includes a substrate with a device region defined thereon. A gate stack is disposed on the substrate in the device region. A channel region is located in the substrate beneath the gate stack, while a first diffusion region is located in the substrate on a first side of the gate stack. A first isolation structure in the substrate, located on the first side of the gate stack, separates the channel and the first diffusion region. The high voltage device also includes a first drift region in the substrate coupling the channel to the first diffusion region, wherein the first drift region comprises a non-uniform depth profile conforming to a profile of the first isolation structure.

摘要翻译： 高压器件包括其上限定有器件区域的衬底。 栅极堆叠设置在器件区域中的衬底上。 沟道区域位于栅堆叠下方的衬底中，而第一扩散区位于栅层叠的第一侧上的衬底中。 位于栅极堆叠的第一侧的衬底中的第一隔离结构分离通道和第一扩散区域。 高电压装置还包括在衬底中的第一漂移区域，其将沟道耦合到第一扩散区域，其中第一漂移区域包括符合第一隔离结构的轮廓的不均匀的深度分布。

公开(公告)号：US08222130B2

公开(公告)日：2012-07-17

申请号：US12500620

申请日：2009-07-10

申请人： Guowei Zhang ,  Purakh Raj Verma

发明人： Guowei Zhang ,  Purakh Raj Verma

IPC分类号： H01L21/22

CPC分类号： H01L29/0847 ,  H01L21/26586 ,  H01L21/823807 ,  H01L27/0922 ,  H01L29/0653 ,  H01L29/1045 ,  H01L29/66659 ,  H01L29/7835

摘要： A method of forming a device is presented. The method includes providing a substrate prepared with an active device region. The active device region includes gate stack layers of a gate stack including at least a gate electrode layer over a gate dielectric layer. A first mask is provided on the substrate corresponding to the gate. The substrate is patterned to at least remove portions of a top gate stack layer unprotected by the first mask. A second mask is also provided on the substrate with an opening exposing a portion of the first mask and the top gate stack layer. A channel well is formed by implanting ions through the opening and gate stack layers into the substrate.

摘要翻译： 提出了一种形成装置的方法。 该方法包括提供用活性器件区域制备的衬底。 有源器件区域包括至少包括栅极电介质层上的栅极电极层的栅极堆叠的栅极堆叠层。 在对应于栅极的基板上设置第一掩模。 将衬底图案化以至少去除未被第一掩模保护的顶部栅极堆叠层的部分。 在基板上还设有第二掩模，该开口具有暴露第一掩模和顶栅层叠层的一部分的开口。 通过将离子通过开口和栅极堆叠层注入衬底而形成通道阱。

公开(公告)号：US07488662B2

公开(公告)日：2009-02-10

申请号：US11302479

申请日：2005-12-13

申请人： Shaoqiang Zhang ,  Purakh Raj Verma ,  Sanford Chu

发明人： Shaoqiang Zhang ,  Purakh Raj Verma ,  Sanford Chu

IPC分类号： H01L21/331

CPC分类号： H01L21/82285 ,  H01L21/8249 ,  H01L27/0623 ,  H01L27/0826 ,  H01L29/7378

摘要： A structure and a process for a self-aligned vertical PNP transistor for high performance SiGe CBiCMOS process. Embodiments include SiGe CBiCMOS with high-performance SiGe NPN transistors and PNP transistors. As the PNP transistors and NPN transistors contained different types of impurity profile, they need separate lithography and doping step for each transistor. The process is easy to integrate with existing CMOS process to save manufacturing time and cost. As plug-in module, fully integration with SiGe BiCMOS processes. High doping Polysilicon Emitter can increase hole injection efficiency from emitter to base, reduce emitter resistor, and form very shallow EB junction. Self-aligned N+ base implant can reduce base resistor and parasitical EB capacitor. Very low collector resistor benefits from BP layer. PNP transistor can be Isolated from other CMOS and NPN devices by BNwell, Nwell and BN+ junction.

摘要翻译： 用于高性能SiGe CBiCMOS工艺的自对准垂直PNP晶体管的结构和工艺。 实施例包括具有高性能SiGe NPN晶体管和PNP晶体管的SiGe CBiCMOS。 由于PNP晶体管和NPN晶体管包含不同类型的杂质分布，因此每个晶体管需要单独的光刻和掺杂步骤。 该过程易于与现有的CMOS工艺集成，以节省制造时间和成本。 作为插件模块，与SiGe BiCMOS工艺完全集成。 高掺杂多晶硅发射器可以增加从发射极到基极的空穴注入效率，减少发射极电阻，并形成非常浅的EB结。 自对准N +基极植入可以减少基极电阻和寄生EB电容。 极低的集电极电阻受益于BP层。 PNP晶体管可以通过BNwell，Nwell和BN +结与其他CMOS和NPN器件隔离。

公开(公告)号：US20080246071A1

公开(公告)日：2008-10-09

申请号：US11696736

申请日：2007-04-05

申请人： Manju Sarkar ,  Purakh Raj Verma

发明人： Manju Sarkar ,  Purakh Raj Verma

IPC分类号： H01L29/94 ,  H01L21/334 ,  H01L31/00

CPC分类号： H01L29/93 ,  H01L29/66189 ,  H01L29/94

摘要： A MOS varactor includes a shallow PN junction beneath the surface of the substrate of a MOS structure. In depletion mode, the depletion region of the MOS structure merges with the depletion region of the shallow PN junction. This increases the total width of the depletion region of the MOS varactor to reduce Cmin.

摘要翻译： MOS变容二极管包括在MOS结构的衬底的表面下面的浅PN结。 在耗尽模式中，MOS结构的耗尽区与浅PN结的耗尽区相结合。 这增加了MOS变容二极管的耗尽区的总宽度以减少C min min。