公开(公告)号：US06614274B1

公开(公告)日：2003-09-02

申请号：US10063836

申请日：2002-05-17

申请人： Bingxue Shi ,  Baoyong Chi

发明人： Bingxue Shi ,  Baoyong Chi

IPC分类号： H03K2500

CPC分类号： H03K23/667

摘要： A novel 2/3 full-speed divider operating at high speed with low power consumption comprising a ECL D flip-flop in master-slave configuration and a phases-selection block is provided in the present invention. The master latch and slave latch comprise a pair of input terminals, a pair of control terminals, and a pair of output terminals. The master latch further comprises two pairs of complementary cross-couple transistors for amplifying the output of the master latch for entering the phase-selection block. The phase-selection block has a pair of input terminals, a clock signal input terminal, and an output terminal generating an output signal adjusted by a division ratio according to the clock signal. The division ratio is either 1/2 or 1/3 and the divider functions as a 2/3 divider.

摘要翻译： 在本发明中提供了一种新型的2/3全速分频器，其具有低功耗，包括主从配置中的ECL D触发器和相位选择块。 主锁存器和从锁存器包括一对输入端子，一对控制端子和一对输出端子。 主锁存器还包括两对互补的交叉耦合晶体管，用于放大用于输入相位选择块的主锁存器的输出。 相位选择块具有一对输入端子，时钟信号输入端子和输出端子，用于根据时钟信号产生由分频比调整的输出信号。 分频比为1/2或1/3，分频器用作2/3分频器。

公开(公告)号：US06242953B1

公开(公告)日：2001-06-05

申请号：US09480325

申请日：2000-01-10

申请人： John C. Thomas

发明人： John C. Thomas

IPC分类号： H03K2500

CPC分类号： G06F1/08 ,  H03K5/135 ,  H03L7/00

摘要： Multiplexers are used to generate synchronized slave clocks from a common master clock. A first multiplexer and a second multiplexer generate a first slave clock and a second slave clock, respectively, from the common master clock. A third multiplexer and a fourth multiplexer are configured as a divide-by-n circuit for providing a third slave clock that is a divided version of the second slave clock. A fifth multiplexer provides a matching delay to preserve the synchronization between the first slave clock and the other slave clocks. A sixth multiplexer is used to select between the second slave clock and the third slave clock in response to a select signal. A flip-flop may be used to provide the select signal and to guard against false selection of slave clocks.

摘要翻译： 多路复用器用于从公共主时钟生成同步的从时钟。 第一多路复用器和第二多路复用器分别从公共主时钟产生第一从时钟和第二从时钟。 第三多路复用器和第四多路复用器被配置为用于提供作为第二从时钟的分割版本的第三从时钟的分频电路。 第五复用器提供匹配延迟以保持第一从时钟和其它从时钟之间的同步。 第六多路复用器用于响应于选择信号在第二从时钟和第三从时钟之间进行选择。 可以使用触发器来提供选择信号并防止从属时钟的错误选择。

公开(公告)号：US06570417B2

公开(公告)日：2003-05-27

申请号：US09982844

申请日：2001-10-22

申请人： Ka Lun Choi ,  Derek Hing Sang Tam

发明人： Ka Lun Choi ,  Derek Hing Sang Tam

IPC分类号： H03K2500

CPC分类号： H03K23/546

摘要： A frequency dividing circuit divides a master clock frequency by a non-integer factor to provide an output clock signal whose frequency is equal to the frequency of the master clock signal divided by that non-integer factor. In one embodiment, the circuit is operative to divide the master clock frequency by 2.5.

公开(公告)号：US06462595B1

公开(公告)日：2002-10-08

申请号：US09626395

申请日：2000-07-26

申请人： June-Ming Hsu ,  Shen Juan Liu

发明人： June-Ming Hsu ,  Shen Juan Liu

IPC分类号： H03K2500

CPC分类号： H03K23/667

摘要： A low-voltage divide-by-64/65 prescaler fabricated with a 0.35 &mgr;m standard CMOS technology is presented to lower power dissipation. A new dynamic D-flip-flop (DFF) using the dynamic back-gate forward bias method has been developed for low-voltage operation. The prescaler including a preamplifier measured at 1 V supply voltage has a maximum operating frequency of 170 MHz and its power dissipation is only 0.9 mW.

摘要翻译： 提供了采用0.35 mum标准CMOS技术制造的低压除以64/65预分频器，以降低功耗。 已经开发了一种使用动态背栅正向偏置法的新型动态D触发器（DFF），用于低电压工作。 包括在1 V电源电压下测量的前置放大器的预分频器的最大工作频率为170 MHz，其功耗仅为0.9 mW。

公开(公告)号：US06765418B2

公开(公告)日：2004-07-20

申请号：US10099276

申请日：2002-03-14

申请人： Glenn Keiji Murata

发明人： Glenn Keiji Murata

IPC分类号： H03K2500

CPC分类号： H03K21/02

摘要： A single-phase clock CLK0 is divided into a clock signal CLK1 to drive nMOS transistor and a clock signal CLK2 to drive pMOS transistor, and the resulting clock signals are inputted to DFF circuits 1 to 3 constituting a frequency dividing circuit, making gms of nMOS and pMOS transistors larger than that could be achieved using the conventional technique. Therefore, frequency dividing performance can be greatly improved in comparison with that achieved using conventional technology.

摘要翻译： 单相时钟CLK0被分成时钟信号CLK1以驱动nMOS晶体管和时钟信号CLK2以驱动pMOS晶体管，并且所得到的时钟信号被输入到构成分频电路的DFF电路1至3，使得gms为nMOS 并且使用传统技术可以实现比这更大的pMOS晶体管。 因此，与使用传统技术的分频性能相比，可以大大提高分频性能。

公开(公告)号：US06639435B2

公开(公告)日：2003-10-28

申请号：US10200635

申请日：2002-07-22

申请人： Josef Hölzle

发明人： Josef Hölzle

IPC分类号： H03K2500

CPC分类号： H03K23/66 ,  H03K21/00

摘要： The novel frequency divider has an adjustable divider ratio. Such circuits are subject to demands for ever higher clock frequencies. The circuit generates the output signal in a blockwise manner and converts it into a sequential signal in a parallel-serial converter on the output side and outputs it in a bitwise manner. As a result, the essential part of the frequency divider circuit can be operated with a slower frequency than the input frequency, which in turn enables higher input frequencies.

摘要翻译： 新颖的分频器具有可调的分频比。 这样的电路需要更高的时钟频率。 该电路以块状方式产生输出信号，并将其转换为输出侧的并行 - 串行转换器中的顺序信号，并以比特方式输出。 结果，分频器电路的基本部分可以以比输入频率更低的频率工作，这进而能够实现更高的输入频率。

公开(公告)号：US06281712B1

公开(公告)日：2001-08-28

申请号：US09654698

申请日：2000-09-05

申请人： Frederick L. Martin ,  Jeremy Marks

发明人： Frederick L. Martin ,  Jeremy Marks

IPC分类号： H03K2500

CPC分类号： H03L7/087 ,  H03D13/004 ,  H03L7/089 ,  H03L7/113

摘要： A phase detector circuit (100) operating at a high frequency includes a steering circuit (112) operating on frequency-divided versions of the phase detector signals. The phase detector (100) implements steering by adding dividers (108, 110) at both input ports to the steering circuit (112). This achieves the desired effect of reducing the operating frequency of the input signals to the steering circuit (112) to make operation possible at high frequencies of operation. The phase detector (100) also allows the steer circuit (112) to be turned off in steady state operation, this is accomplished by coupling only the steer outputs of the steering circuit (12) to the tuning line. The phase/frequency detect outputs are not coupled to the tuning line.

摘要翻译： 以高频工作的相位检测器电路（100）包括在相位检测器信号的分频版本上工作的转向电路（112）。 相位检测器（100）通过在转向电路（112）的两个输入端口处加上分频器（108,110）来实现转向。 这实现了将输入信号的操作频率降低到转向电路（112）以使得在高操作频率下可操作的期望效果。 相位检测器（100）还允许转向电路（112）在稳态操作中被关闭，这通过仅将转向电路（12）的转向输出与调谐线相连来实现。 相位/频率检测输出不耦合到调谐线。