公开(公告)号：US07428287B2

公开(公告)日：2008-09-23

申请号：US10491947

申请日：2002-08-26

申请人： Josef Hölzle

发明人： Josef Hölzle

IPC分类号： H04L7/00 ,  H03D3/24

CPC分类号： H04L7/0054 ,  G06F1/10 ,  H03L7/0814 ,  H04L7/0008

摘要： For synchronising the data transmission between a CMOS circuit (1) and a bipolar circuit (2) a DLL (delayed lock loop) is provided which sets a phase deviation between the operating clocks (CLK1, CLK2) of the two circuits (1, 2), and changes the phase of at least one of the two clocks (CLK1, CLK2) according to this phase deviation, until the two clocks are in phase, in such a way that the data (DATA1) provided by the first circuit (1) can then be taken on by the second circuit (2). To this end, the DLL circuit comprises a phase detector (6), a loop filter (7) and an adjustable element (8).

摘要翻译： 为了同步CMOS电路（1）和双极电路（2）之间的数据传输，提供了一个DLL（延迟锁定环路），其设置两个电路（1）的工作时钟（CLK 1，CLK 2）之间的相位偏差 ，2），并且根据该相位偏差改变两个时钟（CLK 1，CLK 2）中的至少一个的相位，直到两个时钟同相为止，使得由数据（DATA 1）提供的数据 第一电路（1）可以由第二电路（2）接通。 为此，DLL电路包括相位检测器（6），环路滤波器（7）和可调元件（8）。

公开(公告)号：US07242228B2

公开(公告)日：2007-07-10

申请号：US11227987

申请日：2005-09-15

申请人： Josef Hölzle

发明人： Josef Hölzle

IPC分类号： H03L7/06

CPC分类号： H03K5/13 ,  H03K2005/00286 ,  H03L7/0812 ,  H03L7/0891

摘要： An output signal is generated with a predetermined phase shift with respect to an input signal using a closed loop control. The input and output signal of the closed loop control are logically combined in accordance with first and second combinatory logic to generate first and second control signals. The first and second control signals selectively activate first and second current sources, respectively. The current supplied by the first current source charges a capacitance controlling the closed loop control, while the current supplied by the second current source discharges the capacitance. By selecting the types of the combinatory logics as well as the ratio of the currents supplied by the first and second current sources, the phase shift of the output signal with respect to the input signal can be variably adapted to individual requirements.

摘要翻译： 使用闭环控制相对于输入信号以预定的相移产生输出信号。 根据第一和第二组合逻辑逻辑地组合闭环控制的输入和输出信号以产生第一和第二控制信号。 第一和第二控制信号分别选择性地激活第一和第二电流源。 由第一电流源提供的电流对控制闭环控制的电容充电，而由第二电流源提供的电流放电电容。 通过选择组合逻辑的类型以及由第一和第二电流源提供的电流的比率，输出信号相对于输入信号的相移可以可变地适应于个体需求。

公开(公告)号：US06639435B2

公开(公告)日：2003-10-28

申请号：US10200635

申请日：2002-07-22

申请人： Josef Hölzle

发明人： Josef Hölzle

IPC分类号： H03K2500

CPC分类号： H03K23/66 ,  H03K21/00

摘要： The novel frequency divider has an adjustable divider ratio. Such circuits are subject to demands for ever higher clock frequencies. The circuit generates the output signal in a blockwise manner and converts it into a sequential signal in a parallel-serial converter on the output side and outputs it in a bitwise manner. As a result, the essential part of the frequency divider circuit can be operated with a slower frequency than the input frequency, which in turn enables higher input frequencies.

摘要翻译： 新颖的分频器具有可调的分频比。 这样的电路需要更高的时钟频率。 该电路以块状方式产生输出信号，并将其转换为输出侧的并行 - 串行转换器中的顺序信号，并以比特方式输出。 结果，分频器电路的基本部分可以以比输入频率更低的频率工作，这进而能够实现更高的输入频率。