公开(公告)号：US07026880B2

公开(公告)日：2006-04-11

申请号：US10846712

申请日：2004-05-13

申请人： Bingxue Shi ,  Baoyong Chi

发明人： Bingxue Shi ,  Baoyong Chi

IPC分类号： H03B5/02

CPC分类号： H03B27/00 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/1243 ,  H03B5/1293 ,  H03B2201/0208

摘要： A quadrature VCO includes two cross-coupled differential pairs, two parallel LC tank circuits, two LO units and a plurality of source followers, supplying by a tail current source and a tail capacitor. The LC tank circuit constitutes of symmetrical spiral inductors and differential varactors, which constitutes of common anode diodes. The quadrature VCO circuitry is implemented on a chip with 2.4 GHz operating frequency. The quadrature VCO generates quadrature LO signals with high phase accuracy and good gain match under low power, good phase noise and small chip area, thus it can be applied to a variety of integrated transceivers.

摘要翻译： 正交VCO包括两个交叉耦合差分对，两个并联LC谐振电路，两个LO单元和多个源跟随器，由尾电流源和尾电容器提供。 LC谐振电路由对称的螺旋电感器和微分可变电抗器组成，构成常见的阳极二极管。 正交VCO电路在2.4GHz工作频率的芯片上实现。 正交VCO产生具有高相位精度的正交LO信号，在低功率，良好的相位噪声和小芯片面积下具有良好的增益匹配，因此可以应用于各种集成收发器。

公开(公告)号：US20050270081A1

公开(公告)日：2005-12-08

申请号：US10860223

申请日：2004-06-03

申请人： Bingxue Shi ,  Baoyong Chi

发明人： Bingxue Shi ,  Baoyong Chi

IPC分类号： H03D7/14 ,  H03G3/20

CPC分类号： H03D7/1441 ,  H03D7/1458 ,  H03D2200/0023 ,  H03D2200/0043

摘要： A down-converter and a testing device for the down-converter are provided. The down-converter implements a Class-AB single-end input, differential output double balanced mixer structure. By introducing an on-chip bias loop, it significantly improves the symmetry and linearity of the mixer. The down-converter on-chip implements an input impedance match circuit and an open-drain output stage. By optimizing the circuit structure and each device, it achieves the objectives of a high conversion gain, high linearity, and low noise coefficient.

摘要翻译： 提供下变频器和下变频器的测试装置。 下变频器实现了AB类单端输入，差分输出双平衡混频器结构。 通过引入片上偏置环，它显着提高了混频器的对称性和线性。 片上下变频器实现了输入阻抗匹配电路和开漏输出级。 通过优化电路结构和每个器件，实现了高转换增益，高线性度和低噪声系数的目标。

公开(公告)号：US20050253660A1

公开(公告)日：2005-11-17

申请号：US10846712

申请日：2004-05-13

申请人： Bingxue Shi ,  Baoyong Chi

发明人： Bingxue Shi ,  Baoyong Chi

IPC分类号： H03B1/00 ,  H03B5/12 ,  H03B27/00

CPC分类号： H03B27/00 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/1243 ,  H03B5/1293 ,  H03B2201/0208

摘要： A quadrature VCO includes two cross-coupled differential pairs, two parallel LC tank circuits, two LO units and a plurality of source followers, supplying by a tail current source and a tail capacitor. The LC tank circuit constitutes of symmetrical spiral inductors and differential varactors, which constitutes of common anode diodes. The quadrature VCO circuitry is implemented on a chip with 2.4 GHz operating frequency. The quadrature VCO generates quadrature LO signals with high phase accuracy and good gain match under low power, good phase noise and small chip area, thus it can be applied to a variety of integrated transceivers.

摘要翻译： 正交VCO包括两个交叉耦合差分对，两个并联LC谐振电路，两个LO单元和多个源跟随器，由尾电流源和尾电容器提供。 LC谐振电路由对称的螺旋电感器和微分可变电抗器组成，构成常见的阳极二极管。 正交VCO电路在2.4GHz工作频率的芯片上实现。 正交VCO产生具有高相位精度的正交LO信号，在低功率，良好的相位噪声和小芯片面积下具有良好的增益匹配，因此可以应用于各种集成收发器。

公开(公告)号：US07248665B2

公开(公告)日：2007-07-24

申请号：US10908074

申请日：2005-04-27

申请人： Bingxue Shi ,  Baoyong Chi

发明人： Bingxue Shi ,  Baoyong Chi

IPC分类号： H03K21/00

CPC分类号： H03K23/667

摘要： Disclosed is a Dual-Modulus Prescaler (DMP) dividing an input signal into an output signal, comprising: a synchronous counter, including a D-Flip-Flop (DFF), a first NOR-Flip-Flop and a second NOR-Flip-Flop, receiving the input signal, the division ratio thereof being based on an intermediate signal; a control logic, controlling the division ratio of the synchronous counter and selecting the output frequency based on first and second control signals, and outputting the intermediate signal to the synchronous counter; and an asynchronous counter, coupled to the control logic and the synchronous counter, having a chain of five DFFs.

摘要翻译： 公开了一种将输入信号分解为输出信号的双模预分频器（DMP），包括：同步计数器，包括D触发器（DFF），第一NOR触发器和第二NOR触发器， 触发器接收输入信号，其分频比基于中间信号; 控制逻辑，控制同步计数器的分频比，并基于第一和第二控制信号选择输出频率，并将中间信号输出到同步计数器; 以及耦合到控制逻辑和同步计数器的异步计数器，具有五个DFF链。

公开(公告)号：US20060245534A1

公开(公告)日：2006-11-02

申请号：US10908074

申请日：2005-04-27

申请人： Bingxue Shi ,  Baoyong Chi

发明人： Bingxue Shi ,  Baoyong Chi

IPC分类号： H03K21/00

CPC分类号： H03K23/667

摘要： Disclosed is a Dual-Modulus Prescaler (DMP) dividing an input signal into an output signal, comprising: a synchronous counter, including a D-Flip-Flop (DFF), a first NOR-Flip-Flop and a second NOR-Flip-Flop, receiving the input signal, the division ratio thereof being based on an intermediate signal; a control logic, controlling the division ratio of the synchronous counter and selecting the output frequency based on first and second control signals, and outputting the intermediate signal to the synchronous counter; and an asynchronous counter, coupled to the control logic and the synchronous counter, having a chain of five DFFs.

摘要翻译： 公开了一种将输入信号分解为输出信号的双模预分频器（DMP），包括：同步计数器，包括D触发器（DFF），第一NOR触发器和第二NOR触发器， 触发器，接收输入信号，其分频比基于中间信号; 控制逻辑，控制同步计数器的分频比，并基于第一和第二控制信号选择输出频率，并将中间信号输出到同步计数器; 以及耦合到控制逻辑和同步计数器的异步计数器，具有五个DFF链。

公开(公告)号：US07049878B2

公开(公告)日：2006-05-23

申请号：US10860223

申请日：2004-06-03

申请人： Bingxue Shi ,  Baoyong Chi

发明人： Bingxue Shi ,  Baoyong Chi

IPC分类号： G06F7/44

CPC分类号： H03D7/1441 ,  H03D7/1458 ,  H03D2200/0023 ,  H03D2200/0043

摘要： A down-converter and a testing device for the down-converter are provided. The down-converter implements a Class-AB single-end input, differential output double balanced mixer structure. By introducing an on-chip bias loop, it significantly improves the symmetry and linearity of the mixer. The down-converter on-chip implements an input impedance match circuit and an open-drain output stage. By optimizing the circuit structure and each device, it achieves the objectives of a high conversion gain, high linearity, and low noise coefficient.

摘要翻译： 提供下变频器和下变频器的测试装置。 下变频器实现了AB类单端输入，差分输出双平衡混频器结构。 通过引入片上偏置环，它显着提高了混频器的对称性和线性。 片上下变频器实现了输入阻抗匹配电路和开漏输出级。 通过优化电路结构和每个器件，实现了高转换增益，高线性度和低噪声系数的目标。

公开(公告)号：US07057421B2

公开(公告)日：2006-06-06

申请号：US10829262

申请日：2004-04-22

申请人： Bingxue Shi ,  Baoyong Chi

发明人： Bingxue Shi ,  Baoyong Chi

IPC分类号： G01R19/00

CPC分类号： H03K3/012 ,  H03K3/356139

摘要： A flipflop. In the flipflop, a differential pair is coupled to two input signals inverse to each other. A first latch unit is connected to the differential pair in parallel, and includes a first node and a second node coupled to generate complementary latch signals according to the first and second data signals. A signal amplification circuit is coupled to the differential pair and the first latch unit to generate complementary amplified signals according to the complementary latch signals. A second latch unit is coupled to the signal amplifier circuit to generate complementary static output signals according to the complementary amplified signals and to maintain the complementary static output signals.

摘要翻译： 触发器。 在触发器中，差分对被耦合到彼此相反的两个输入信号。 第一锁存单元并联连接到差分对，并且包括耦合以根据第一和第二数据信号产生互补锁存信号的第一节点和第二节点。 信号放大电路耦合到差分对和第一锁存单元，以根据互补锁存信号产生互补的放大信号。 第二锁存单元耦合到信号放大器电路，以根据互补的放大信号产生互补的静态输出信号并维持互补的静态输出信号。

公开(公告)号：US20050237096A1

公开(公告)日：2005-10-27

申请号：US10829262

申请日：2004-04-22

申请人： Bingxue Shi ,  Baoyong Chi

发明人： Bingxue Shi ,  Baoyong Chi

IPC分类号： H03K3/00 ,  H03K3/012 ,  H03K3/037 ,  H03K3/356

CPC分类号： H03K3/012 ,  H03K3/356139

摘要： A flipflop. In the flipflop, a differential pair is coupled to two input signals inverse to each other. A first latch unit is connected to the differential pair in parallel, and includes a first node and a second node coupled to generate complementary latch signals according to the first and second data signals. A signal amplification circuit is coupled to the differential pair and the first latch unit to generate complementary amplified signals according to the complementary latch signals. A second latch unit is coupled to the signal amplifier circuit to generate complementary static output signals according to the complementary amplified signals and to maintain the complementary static output signals.

摘要翻译： 触发器。 在触发器中，差分对被耦合到彼此相反的两个输入信号。 第一锁存单元并联连接到差分对，并且包括耦合以根据第一和第二数据信号产生互补锁存信号的第一节点和第二节点。 信号放大电路耦合到差分对和第一锁存单元，以根据互补锁存信号产生互补的放大信号。 第二锁存单元耦合到信号放大器电路，以根据互补放大信号产生互补的静态输出信号并维持互补的静态输出信号。

公开(公告)号：US06614274B1

公开(公告)日：2003-09-02

申请号：US10063836

申请日：2002-05-17

申请人： Bingxue Shi ,  Baoyong Chi

发明人： Bingxue Shi ,  Baoyong Chi

IPC分类号： H03K2500

CPC分类号： H03K23/667

摘要： A novel 2/3 full-speed divider operating at high speed with low power consumption comprising a ECL D flip-flop in master-slave configuration and a phases-selection block is provided in the present invention. The master latch and slave latch comprise a pair of input terminals, a pair of control terminals, and a pair of output terminals. The master latch further comprises two pairs of complementary cross-couple transistors for amplifying the output of the master latch for entering the phase-selection block. The phase-selection block has a pair of input terminals, a clock signal input terminal, and an output terminal generating an output signal adjusted by a division ratio according to the clock signal. The division ratio is either 1/2 or 1/3 and the divider functions as a 2/3 divider.

摘要翻译： 在本发明中提供了一种新型的2/3全速分频器，其具有低功耗，包括主从配置中的ECL D触发器和相位选择块。 主锁存器和从锁存器包括一对输入端子，一对控制端子和一对输出端子。 主锁存器还包括两对互补的交叉耦合晶体管，用于放大用于输入相位选择块的主锁存器的输出。 相位选择块具有一对输入端子，时钟信号输入端子和输出端子，用于根据时钟信号产生由分频比调整的输出信号。 分频比为1/2或1/3，分频器用作2/3分频器。