公开(公告)号：US20230139807A1

公开(公告)日：2023-05-04

申请号：US17515365

申请日：2021-10-29

申请人： KYNDRYL, INC.

发明人： Cesar Augusto RODRIGUEZ BRAVO

IPC分类号： G06F21/85 ,  G06F21/81 ,  G06F21/64 ,  G06F21/57

摘要： Methods, computer program products, and systems are presented. The Methods, computer program products, and systems can include, for example: examining hardware device transmitted data received through an I/O interface port of a computer system; determining in dependence on the examining whether the hardware device transmitted data received through the I/O interface port of the computer system satisfies a criterion; and in response to determining that the hardware device transmitted data received through the I/O interface port of the computer system satisfies the criterion, initiating a security process for protecting the computer system.

公开(公告)号：US20230124797A1

公开(公告)日：2023-04-20

申请号：US18083533

申请日：2022-12-18

申请人： Nicira, Inc.

发明人： Mike Parsa ,  Jayant Jain ,  Xinhua Hong ,  Anirban Sengupta ,  Kai-Wei Fan

IPC分类号： H04L45/00 ,  H04L45/7453 ,  G06F21/85 ,  H04L9/40

摘要： In order to enable dynamic scaling of network services at the edge, novel systems and methods are provided to enable addition of add new nodes or removal of existing nodes while retaining the affinity of the flows through the stateful services. The methods provide a cluster of network nodes that can be dynamically resized to handle and process network traffic that utilizes stateful network services. The existing traffic flows through the edge continue to function during and after the changes to membership of the cluster. All nodes in the cluster operate in active-active mode, i.e., they are receiving and processing traffic flows, thereby maximizing the utilization of the available processing power.

公开(公告)号：US20230116296A1

公开(公告)日：2023-04-13

申请号：US18045717

申请日：2022-10-11

申请人： Google LLC

发明人： David Ness Schneider ,  Alex Levin

IPC分类号： G06F21/57 ,  G06F21/85

摘要： This document describes apparatuses, systems, and techniques directed to a modular system validation platform for computing devices. The modular system validation platform includes an interface board for interfacing a host with a peripheral. The interface board includes an apparatus identifier, a first connector configured to couple to the host, and a second connector configured to couple to the peripheral. The interface board comprises interface circuitry that can be reconfigured to enable different peripherals to operate with the host using the same interface board. The interface circuitry enables the interoperability between the host and the peripheral by distributing power from the host to the peripheral and facilitating communications between the host and the peripheral. By using the reconfigurable interface board to test and troubleshoot the interoperability of the processor and the peripheral, resources, time and costs spent during the design and testing phases of computing devices may be minimized.

公开(公告)号：US20230090728A1

公开(公告)日：2023-03-23

申请号：US17969438

申请日：2022-10-19

申请人： CenturyLink Intellectual Property LLC

发明人： Tom Funk

IPC分类号： G06F21/56 ,  G07C5/00 ,  G07C5/08 ,  H04W76/30 ,  G06F21/85 ,  H04L9/40 ,  H04W24/08 ,  H04W12/122 ,  H04W12/128

摘要： Novel tools and techniques might provide for implementing Internet of Things (“IoT”) functionality, and, in particular embodiments, implementing added services for OBD2 connection for IoT-capable vehicles. In various embodiments, a portable device (when connected to an OBD2 DLC port of a vehicle) might monitor wireless communications between a vehicle computing system(s) and an external device(s), might monitor vehicle sensor data from vehicular sensors tracking operational conditions of the vehicle, and might monitor operator input sensor data from operator input sensors tracking input by a vehicle operator. The portable device (or a server) might analyze either the monitored wireless communications or a combination of the monitored vehicle sensor data and the monitored operator input sensor data, to determine whether vehicle operation has been compromised. If so, the portable device (or the server) might alert the operator of the vehicle via a user interface, and might initiate one or more remediation operations.

公开(公告)号：US11582189B2

公开(公告)日：2023-02-14

申请号：US16632611

申请日：2018-08-22

申请人： Audi AG

发明人： Changsup Ahn ,  Kamil Zawadzki ,  Markus Klein ,  Hans Georg Gruber

IPC分类号： H04L9/40 ,  G06F13/42 ,  G06F21/44 ,  G06F21/60 ,  G06F21/85

摘要： A method for filtering communication data arriving from a communication partner via a communication connection, which provides access to at least one storage means of a receiving data processing device having at least one computation unit, in the data processing device, wherein PCI Express, in an interface unit, receiving the communication data, of the data processing device, a filter means, at least part of which is embodied as hardware, is used so that, according to configuration information, prescribed on the data processing device, containing at least one approval condition that rates the at least one property of the useful data contained in the communication data, only the communication data meeting at least one approval condition are forwarded from the interface unit to at least one further component of the data processing device.

公开(公告)号：US20230018185A1

公开(公告)日：2023-01-19

申请号：US17950493

申请日：2022-09-22

申请人： Arm Limited

发明人： Michael WEINER ,  Oded GOLOMBEK ,  Harel ADANI

IPC分类号： H04L9/00 ,  G06F21/60 ,  G06F21/85

摘要： A method for obfuscating data at-transit can include receiving, at a first component on a chip, an instruction request for communicating a first data to a second component on the chip. The first component can be a processor and the second component can be an associated memory. The method can further include, determining a sequence of data arranged to obfuscate the first data while including valid bits of the first data, wherein the sequence of data indicates what is to be conveyed across lines on the chip during each time slot over a window of time controlled by a clock signal on the chip; and providing, over the window of time, the first data to the second component across the lines on the chip according to the sequence of data.

公开(公告)号：US11556677B2

公开(公告)日：2023-01-17

申请号：US17132306

申请日：2020-12-23

申请人： Intel Corporation

发明人： Furkan Turan ,  Patrick Koeberl ,  Alpa Trivedi ,  Steffen Schulz ,  Scott Weber

IPC分类号： G06F30/398 ,  G06F21/85 ,  G06N3/04 ,  H04L9/08 ,  G06F9/30 ,  G06F9/50 ,  G06F15/177 ,  G06F15/78 ,  H04L9/40 ,  G06F11/07 ,  G06F30/331 ,  G06F9/38 ,  G06F11/30 ,  G06F119/12 ,  G06F21/76 ,  G06N3/08 ,  H04L9/00 ,  G06F111/04 ,  G06F30/31 ,  G06F21/30 ,  G06F21/53 ,  G06F21/57 ,  G06F21/73 ,  G06F21/74 ,  G06N20/00 ,  G06F21/71 ,  G06F21/44

摘要： An apparatus to facilitate scalable runtime validation for on-device design rule checks is disclosed. The apparatus includes a memory to store a contention set, one or more multiplexors, and a validator communicably coupled to the memory. In one implementation, the validator is to: receive design rule information for the one or more multiplexers, the design rule information referencing the contention set; analyze, using the design rule information, a user bitstream against the contention set at a programming time of the apparatus, the user bitstream for programming the one or more multiplexors; and provide an error indication responsive to identifying a match between the user bitstream and the contention set.

公开(公告)号：US11544413B2

公开(公告)日：2023-01-03

申请号：US17051760

申请日：2019-05-02

申请人： Nordic Semiconductor ASA

发明人： Frank Aune ,  Jean-Baptiste Brelot

IPC分类号： G06F21/79 ,  G06F21/60 ,  G06F21/72 ,  G06F21/74 ,  G06F21/85

摘要： An integrated-circuit device comprises a processor, a hardware key-storage system, and a key bus. The hardware key-storage system comprises a non-volatile key storage memory, which includes a key register, for storing a cryptographic key, and an address register, for storing a destination memory address for the cryptographic key. The hardware key-storage system further comprises output logic for sending the cryptographic key over the key bus to the destination memory address, and write-once logic for preventing an address being written to the address register unless the address register is in an erased state.

公开(公告)号：US20220414274A1

公开(公告)日：2022-12-29

申请号：US17359930

申请日：2021-06-28

申请人： BAE Systems Information and Electronic Systems Integration Inc.

发明人： Michael J. Weber

IPC分类号： G06F21/85 ,  G06F21/55 ,  G06F21/56

摘要： Techniques are provided for actively controlling a communications bus to mitigate threats, including cyber-attacks. A methodology implementing the techniques according to an embodiment includes detecting a threat in a message that is being transmitted between nodes on the communications bus. The message comprises one or more message frames and the threat detection is based on analysis of an initial portion of the message frame. The method further includes actively controlling the bus, based on the threat detection, to prevent the remaining portion of the message frame from delivering the threat to one or more of the nodes on the bus. Actively controlling the bus includes isolating nodes from the bus and/or overwriting data in the remaining portion of the message frame to invalidate the message frame or to remove the threat from the message frame.

公开(公告)号：US11537761B2

公开(公告)日：2022-12-27

申请号：US17129254

申请日：2020-12-21

申请人： Intel Corporation

发明人： Steffen Schulz ,  Alpa Trivedi ,  Patrick Koeberl

IPC分类号： G06F21/85 ,  G06F9/30 ,  G06F9/50 ,  G06F15/177 ,  G06F15/78 ,  G06F30/331 ,  G06F30/398 ,  G06N3/04 ,  H04L9/08 ,  H04L9/40 ,  G06F11/07 ,  G06F9/38 ,  G06F11/30 ,  G06F119/12 ,  G06F21/76 ,  G06N3/08 ,  H04L9/00 ,  G06F111/04 ,  G06F30/31 ,  G06F21/30 ,  G06F21/53 ,  G06F21/57 ,  G06F21/73 ,  G06F21/74 ,  G06N20/00 ,  G06F21/71 ,  G06F21/44

摘要： An apparatus to facilitate transparent network access controls for spatial accelerator device multi-tenancy is disclosed. The apparatus includes a secure device manager (SDM) to: establish a network-on-chip (NoC) communication path in the apparatus, the NoC communication path comprising a plurality of NoC nodes for ingress and egress of communications on the NoC communication path; for each NoC node of the NoC communication path, configure a programmable register of the NoC node to indicate a node group that the NoC node is assigned, the node group corresponding to a persona configured on the apparatus; determine whether a prefix of received data at the NoC node matches the node group indicated by the programmable register of the NoC; and responsive to determining that the prefix does not match the node group, discard the data from the NoC node.