Data processing circuit for neural network

    公开(公告)号:US12014264B2

    公开(公告)日:2024-06-18

    申请号:US17005488

    申请日:2020-08-28

    摘要: A data processing circuit is disclosed. The data processing circuit relates to the field of digital circuits, and includes a first computing circuit and an input control circuit. The first computing circuit includes one or more computing sub-circuits. Each computing sub-circuit includes a first addition operation circuit, a multiplication operation circuit, a first comparison operation circuit, and a first nonlinear operation circuit. The first nonlinear operation circuit includes at least one of an exponential operation circuit and a logarithmic operation circuit. The input control circuit is configured to: control the first computing circuit to read input data and an input parameter, and control, according to a received first instruction, the operation circuit in the computing sub-circuit included in the first computing circuit, to perform an operation on the input data and the input parameter.

    CONSTANT DIVISION AND MODULO VIA CARRYSAVE MODULO REDUCTION

    公开(公告)号:US20240134603A1

    公开(公告)日:2024-04-25

    申请号:US18396437

    申请日:2023-12-26

    申请人: Intel Corporation

    摘要: The techniques described in the detailed description above enable the manufacturing of circuits with increased performance and efficiency when performing division by a constant number. One embodiment provides circuitry including an input circuit to receive an input value including a plurality of bits, a logarithmic tree coupled with the input circuit, the logarithmic tree configured to compute an array of values based on a plurality of multi-bit groups of the plurality of bits of the input value, each value in the array of values includes a modulus of a corresponding multi-bit group with respect to the constant, a binary array adder to compute a quotient of the division operation based on the array of values, the input value, and the constant, and an output circuit to output the quotient.

    Floating-Point Execution Circuitry for Subset of Binary Logarithm Input Range

    公开(公告)号:US20240061650A1

    公开(公告)日:2024-02-22

    申请号:US17820766

    申请日:2022-08-18

    申请人: Apple Inc.

    IPC分类号: G06F7/556 G06F7/487

    CPC分类号: G06F7/556 G06F7/4873

    摘要: Techniques are disclosed relating to polynomial approximation of the base-2 logarithm. In some embodiments, floating-point circuitry is configured to perform an approximation of a base-2 logarithm operation and provide a fixed unit of least precision (ULP) error over a range of inputs. In some embodiments, the floating-point circuitry includes a set of parallel pipelines for polynomial approximation, where the output is chosen from a particular pipeline based on a determination of whether the input operand is in a first subset of a range of inputs. Disclosed techniques may advantageously provide fixed ULP error for an entire input operand range for the floating-point base-2 logarithmic function with minimal area and energy footprint, relative to traditional techniques.

    Method for measuring distance by appropriate fourier transform and radar system for implementing the method

    公开(公告)号:US11604270B2

    公开(公告)日:2023-03-14

    申请号:US16712864

    申请日:2019-12-12

    申请人: THALES

    摘要: A radar system configured to determine radar-ground distance measurements. The radar system includes transmission and reception means configured to transmit two radiofrequency signals towards the ground and to receive the signals obtained by the reflection of the two transmitted signals by the ground and computation means configured to determine the frequential representations of the transmitted signals and of the received signals and determine a frequential quantity as a function of the frequential representations. The radar system is wherein the computation means are configured to sample the frequential quantity over a determined number of samples, which provides a sampled signal; determine a number of frequency measurements as a function of a constant distance measurement accuracy value; determine frequency measurements by applying to the sampled signal a spectral decomposition by fast Fourier transform using a decimation of the sampled signal in a ratio dependent on the distance measurement accuracy value, and determine a distance measurement corresponding to each frequency measurement.

    DUAL EXPONENT BOUNDING BOX FLOATING-POINT PROCESSOR

    公开(公告)号:US20230037227A1

    公开(公告)日:2023-02-02

    申请号:US17381124

    申请日:2021-07-20

    IPC分类号: G06F7/556 G06F5/01 G06N3/08

    摘要: Apparatus and methods are disclosed for performing matrix operations, including operations suited to neural network and other machine learning accelerators and applications, using dual exponent formats. Disclosed matrix formats include single exponent bounding box floating-point (SE-BBFP) and dual exponent bounding box floating-point (DE-BBFP) formats. Shared exponents for each element are determined for each element based on whether the element is used as a row of matrix tile or a column of a matrix file, for example, for a dot product operation. Computing systems suitable for employing such neural networks include computers having general-purpose processors, neural network accelerators, or reconfigure both logic devices, such as Field programmable gate arrays (FPGA). Certain techniques disclosed herein can provide improved system performance while reducing memory and network bandwidth used.

    Method, device, and program product for determining model compression rate

    公开(公告)号:US11507782B2

    公开(公告)日:2022-11-22

    申请号:US16824834

    申请日:2020-03-20

    摘要: A method for determining a model compression rate comprises determining a near-zero importance value subset from an importance value set associated with a machine learning model, a corresponding importance value in the importance value set indicating an importance degree of a corresponding input of a processing layer of the machine learning model, importance values in the near-zero importance value subset being closer to zero than other importance values in the importance value set; determining a target importance value from the near-zero importance value subset, the target importance value corresponding to a turning point of a magnitude of the importance values in the near-zero importance value subset; determining a proportion of importance values less than the target importance value in the importance value set in the importance value set; and determining the compression rate for the machine learning model based on the determined proportion.

    Compression techniques for vertices of graphic models

    公开(公告)号:US11461275B2

    公开(公告)日:2022-10-04

    申请号:US16692840

    申请日:2019-11-22

    申请人: Apple Inc.

    摘要: Methods for lossy and lossless pre-processing of image data. In one embodiment, a method for lossy pre-processing image data, where the method may include, at a computing device: receiving the image data, where the image data includes a model having a mesh, the mesh includes vertices defining a surface, the vertices including attribute vectors, and the attribute vectors including values. The method also including quantizing the values of the attribute vectors to produce modified values, where a precision of the modified values is determined based on a largest power determined using a largest exponent of the values, encoding pairs of the modified values into two corresponding units of information. The method also including, for each pair of the pairs of the modified values, serially storing the two corresponding units of information as a data stream into a buffer, and compressing the data stream in the buffer.