公开(公告)号：WO2006044743A2

公开(公告)日：2006-04-27

申请号：PCT/US2005/037165

申请日：2005-10-13

Applicant: INTEL CORPORATION ,  HUGGAHALLI, Ramakrishna ,  BATSON, Brannon ,  TETRICK, Raymond ,  BLANKENSHIP, Robert

Inventor： HUGGAHALLI, Ramakrishna ,  BATSON, Brannon ,  TETRICK, Raymond ,  BLANKENSHIP, Robert

IPC: G06F9/38 ,  G06F12/08

CPC classification number: G06F9/383 ,  G06F9/345 ,  G06F12/0862 ,  G06F2212/6028

Abstract: An arrangement is provided for an external agent to initiate data prefetches from a system memory to a cache associated with a target processor, which needs the data to execute a program, in a computing system. When the external agent has data, it may create and issue a prefetch directive. The prefetch directive may be sent along with system interconnection transactions or sent as a separate transaction to devices including the target processor in the system. When receiving and recognizing the prefetch directive, a hardware prefetcher associated with the target processor may issue a request to the system memory to prefetch data to the cache. The target processor can access data in the cache more efficiently than it accesses data in the system memory. Some pre-processing may also be associated with the data prefetch.

Abstract translation: 提供了一种用于外部代理在计算系统中启动从系统存储器到与目标处理器相关联的高速缓存（其需要数据执行程序）的安排。 外部代理具有数据时，可能会创建并发出预取指令。 预取指令可以与系统互连事务一起发送，或作为单独事务发送到包括系统中的目标处理器的设备。 当接收和识别预取指令时，与目标处理器相关联的硬件预取器可以向系统存储器发出请求以将数据预取到高速缓存。 目标处理器可以比访问系统内存中的数据更有效地访问高速缓存中的数据。 一些预处理也可能与数据预取相关联。

公开(公告)号：WO2013165357A1

公开(公告)日：2013-11-07

申请号：PCT/US2012/035827

申请日：2012-04-30

Applicant: INTEL CORPORATION ,  GARG, Vivek ,  SISTLA, Krishnakanth ,  BLANKENSHIP, Robert ,  MULLA, Dean ,  BORKOWSKI, Daniel G. ,  CONRAD, Shaun ,  SRINIVASA, Ganapati

Inventor： GARG, Vivek ,  SISTLA, Krishnakanth ,  BLANKENSHIP, Robert ,  MULLA, Dean ,  BORKOWSKI, Daniel G. ,  CONRAD, Shaun ,  SRINIVASA, Ganapati

IPC: G06F1/32 ,  G06F15/80 ,  G06F13/14

CPC classification number: G06F1/3203 ,  G06F1/3234 ,  Y02D50/20

Abstract: Methods, apparatus, and systems for implementing coordinated idle power management in glueless and clustered systems. Components for facilitating coordination of package idle power state between sockets in a glueless system such as a server platform include a master entity in one socket (i.e., processor) and a slave entity in each socket participating in the power management coordination. Each slave collects idle status inputs from various sources and when the socket cores are sufficiently idle, it makes a request to the master to enter a deeper idle power state. The master coordinates global power management operations in response to the slave requests, including broadcasting a command with a target latency to all of the slaves to allow the processors to enter reduced power (i.e., idle) states in a coordinated manner. Communications between the entities is facilitated using messages transported over existing interconnects and corresponding protocols, enabling the benefits associated with the disclosed embodiments to be implemented using existing designs.

Abstract translation: 在无缝和集群系统中实现协调空闲电源管理的方法，设备和系统。 在诸如服务器平台的无胶纸系统中的用于促进协调包间歇功率状态的组件包括一个插座（即，处理器）中的主实体和参与电力管理协调的每个插座中的从实体。 每个从机从各种来源收集空闲状态输入，当插座内核足够空闲时，它要求主机进入更深的空闲电源状态。 主机响应于从机请求来协调全局功率管理操作，包括向所有从机广播具有目标延迟的命令，以允许处理器以协调的方式进入降低的功率（即空闲）状态。 使用通过现有互连和相应协议传输的消息来促进实体之间的通信，从而能够使用现有设计实现与公开的实施例相关联的益处。

公开(公告)号：WO2003019386A1

公开(公告)日：2003-03-06

申请号：PCT/US2002/025090

申请日：2002-08-06

Applicant: INTEL CORPORATION (a Delaware Corporation)

Inventor： CRETA, Kenneth ,  BELL, Dennis ,  BLANKENSHIP, Robert ,  CONGDON, Bradford ,  GEORGE, Robert ,  JANUARY, Duane

IPC: G06F12/08

CPC classification number: G06F12/0848 ,  G06F12/0802 ,  G06F12/0833 ,  G06F13/4059

Abstract: A caching input/output hub includes a host interface to connect with a host. At least one input/output interface is provided to connect with an input/output device. A write cache manages memory writes initiated by the input/output device. At least one read cache, separate from the write cache, provides a low-latency copy of data that is most likely to be used. The at least one read cache is in communication with the write cache. A cache directory is also provided to track cache lines in the write cache and the at least one read cache. The cache directory is in communication with the write cache and the at least one read cache.

Abstract translation: 缓存输入/输出集线器包括与主机连接的主机接口。 提供至少一个输入/输出接口以与输入/输出设备连接。 写缓存管理由输入/输出设备发起的存储器写入。 与写缓存分开的至少一个读缓存提供了最可能使用的低延迟数据副本。 至少一个读高速缓存与写高速缓存通信。 还提供缓存目录以跟踪写入高速缓存和至少一个读取高速缓存中的高速缓存行。 缓存目录与写缓存和至少一个读高速缓存通信。

公开(公告)号：WO2022139892A1

公开(公告)日：2022-06-30

申请号：PCT/US2021/048847

申请日：2021-09-02

Applicant: INTEL CORPORATION

Inventor： GUPTA, Ritu ,  BLANKENSHIP, Robert

IPC: G06F12/0868 ,  G06F12/0811 ,  G06F12/0815

Abstract: In one embodiment, a system includes an (input/output) I/O domain and a compute domain. The I/O domain includes an I/O agent and a I/O domain caching agent. The compute domain includes a compute domain caching agent and a compute domain cache hierarchy. The I/O agent issues an ownership request to the compute domain caching agent to obtain ownership of a cache line in the compute domain cache hierarchy. In response to the ownership request, the compute domain caching agent places the cache line in the compute domain cache hierarchy in a placeholder state. The placeholder state reserves the cache line for performance of a write operation by the I/O agent. The compute domain caching agent writes data received from the I/O agent to the cache line in the compute domain cache hierarchy and transitions the state of the cache line out of the placeholder state.

公开(公告)号：WO2014098998A1

公开(公告)日：2014-06-26

申请号：PCT/US2013/047279

申请日：2013-06-24

Applicant: INTEL CORPORATION ,  JOHNSON, Simon ,  DAS, Abhishek ,  ROZAS, Carlos ,  SAVAGAONKAR, Uday ,  BLANKENSHIP, Robert ,  PADWEKAR, Kiran

Inventor： JOHNSON, Simon ,  DAS, Abhishek ,  ROZAS, Carlos ,  SAVAGAONKAR, Uday ,  BLANKENSHIP, Robert ,  PADWEKAR, Kiran

IPC: G06F21/60

CPC classification number: H04L9/00 ,  G06F21/556 ,  G06F21/606 ,  H04L9/32 ,  H04L63/0428 ,  H04L63/0471 ,  H04L63/123

Abstract: Embodiments of an invention for securing transmissions between processor packages are disclosed. In one embodiment, an apparatus includes an encryption unit to encrypt first content to be transmitted from the apparatus to a processor package directly through a point-to-point link.

Abstract translation: 公开了用于确保处理器封装之间的传输的发明的实施例。 在一个实施例中，一种装置包括加密单元，用于直接通过点对点链路加密要从装置发送到处理器包的第一内容。