公开(公告)号：WO2023016480A1

公开(公告)日：2023-02-16

申请号：PCT/CN2022/111385

申请日：2022-08-10

Applicant: 华为技术有限公司

Inventor： 陈更 ,  付明 ,  雷继棠

IPC: G06F9/455 ,  G06F12/0815

Abstract: 一种硬件内存序架构下的代码处理方法，应用于计算机系统，尤其适用于在不同的硬件内存序架构下迁移代码的场景。该方法包括获取编译流程中的第一文件，第一文件与源文件关联；将第一文件的目标代码中的volatile内存访问代码转换为atomic内存访问代码，以得到第二文件，目标代码为与并发控制相关的内存访问代码；对第二文件进行编译处理，以得到适用于目标架构的执行文件，目标架构为强内存序架构或弱内存序架构。该方法可以使代码迁移后的执行代码与编写代码保持一致，从而减少了代码运行时出现挂死或死锁等非预期行为。

公开(公告)号：WO2022139892A1

公开(公告)日：2022-06-30

申请号：PCT/US2021/048847

申请日：2021-09-02

Applicant: INTEL CORPORATION

Inventor： GUPTA, Ritu ,  BLANKENSHIP, Robert

IPC: G06F12/0868 ,  G06F12/0811 ,  G06F12/0815

Abstract: In one embodiment, a system includes an (input/output) I/O domain and a compute domain. The I/O domain includes an I/O agent and a I/O domain caching agent. The compute domain includes a compute domain caching agent and a compute domain cache hierarchy. The I/O agent issues an ownership request to the compute domain caching agent to obtain ownership of a cache line in the compute domain cache hierarchy. In response to the ownership request, the compute domain caching agent places the cache line in the compute domain cache hierarchy in a placeholder state. The placeholder state reserves the cache line for performance of a write operation by the I/O agent. The compute domain caching agent writes data received from the I/O agent to the cache line in the compute domain cache hierarchy and transitions the state of the cache line out of the placeholder state.

公开(公告)号：WO2021108388A1

公开(公告)日：2021-06-03

申请号：PCT/US2020/061983

申请日：2020-11-24

Applicant: SIFIVE, INC.

Inventor： TERPSTRA, Wesley Waylon

IPC: G06F12/1045 ,  G06F12/0815

Abstract: Systems and methods are disclosed for virtualized caches. For example, an integrated circuit (e.g., a processor) for executing instructions includes a virtually indexed physically tagged first-level (L1) cache configured to output to an outer memory system one or more bits of a virtual index of a cache access as one or more bits of a requestor identifier. For example, the L1 cache may be configured to operate as multiple logical L1 caches with a cache way of a size less than or equal to a virtual memory page size. For example, the integrated circuit may include an L2 cache of the outer memory system that is configured to receive the requestor identifier and implement a cache coherency protocol to disambiguate an L1 synonym occurring in multiple portions of the virtually indexed physically tagged L1 cache associated with different requestor identifier values.

公开(公告)号：WO2019245612A1

公开(公告)日：2019-12-26

申请号：PCT/US2019/019915

申请日：2019-02-27

Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.

Inventor： DE, Arup

IPC: G06F12/0815 ,  G06F12/0893

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for balanced caching. An input circuit (302) receives (702) a request for data of non-volatile storage. A balancing circuit (304) determines (704) whether to execute a request by directly communicating with one or more of a cache (410) and a non-volatile storage (408) based on a first rate corresponding to the cache (410) and a second rate corresponding to the non-volatile storage (408). A data access circuit (306) executes (706, 708) a request based on a determination made by a balancing circuit (304).

公开(公告)号：WO2019211611A1

公开(公告)日：2019-11-07

申请号：PCT/GB2019/051217

申请日：2019-05-02

Applicant: ARM LIMITED

Inventor： JALAL, Jamshed ,  RINGE, Tushar P ,  MANNAVA, Phanindra Kumar ,  KASERIDIS, Dimitrios

IPC: G06F12/0815

Abstract: An improved protocol for data transfer between a request node and a home node of a data processing network that includes a number of devices coupled via an interconnect fabric is provided that minimizes the number of response messages transported through the interconnect fabric. When congestion is detected in the interconnect fabric, a home node sends a combined response to a write request from a request node. The response is delayed until a data buffer is available at the home node and home node has completed an associated coherence action. When the request node receives a combined response, the data to be written and the acknowledgment are coalesced in the data message.

公开(公告)号：WO2018096313A1

公开(公告)日：2018-05-31

申请号：PCT/GB2017/053370

申请日：2017-11-09

Applicant: ARM LIMITED

Inventor： DUNHAM, Curtis Glenn ,  BEARD, Jonathan Curtis ,  RUSITORU, Roxana

IPC: G06F9/48 ,  G06F9/46 ,  G06F12/0815

Abstract: Data processing apparatus comprises one or more interconnected processing elements; each processing element being configured to execute processing instructions of program tasks; each processing element being configured to save context data relating to a program task following execution of that program task by that processing element; and to load context data, previously saved by that processing element or another of the processing elements, at resumption of execution of a program task; each processing element having respective associated format definition data to define one or more sets of data items for inclusion in the context data; the apparatus comprising format selection circuitry to communicate the format definition data of each of the processing elements with others of the processing elements and to determine, in response to the format definition data for each of the processing elements, a common set of data items for inclusion in the context data.

公开(公告)号：WO2018063729A1

公开(公告)日：2018-04-05

申请号：PCT/US2017/049504

申请日：2017-08-30

Applicant: INTEL CORPORATION

Inventor： DOSHI, Kshitij, A. ,  GUIM BERNAT, Francesc ,  RIVAS BARRAGAN, Daniel

IPC: G06F12/0815

CPC classification number: G06F13/1663 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/067 ,  G06F12/0815 ,  G06F12/1027 ,  G06F12/1433 ,  G06F13/18 ,  G06F2212/1052 ,  G06F2212/68

Abstract: Apparatuses, systems, and methods for coherently sharing data across a multi-node network is described. A coherency protocol for such data sharing can include identifying a memory access request from a requesting node for an I/O block of data in a shared I/O address space of a multi-node network, determining a logical ID and a logical offset of the I/O block, identifying an owner of the I/O block, negotiating permissions with the owner of the I/O block, and performing the memory access request on the I/O block.

Abstract translation: 描述了用于在多节点网络上连贯地共享数据的设备，系统和方法。 用于这种数据共享的一致性协议可以包括识别来自请求节点的针对多节点网络的共享I / O地址空间中的I / O数据块的存储器访问请求，确定逻辑ID和逻辑偏移量 I / O块，识别I / O块的所有者，与I / O块的所有者协商许可，以及在I / O块上执行存储器访问请求。

公开(公告)号：WO2017053086A1

公开(公告)日：2017-03-30

申请号：PCT/US2016/050961

申请日：2016-09-09

Applicant: QUALCOMM INCORPORATED

Inventor： LE, Hien, Minh ,  TRUONG, Thuong, Quang ,  XU, Kun ,  SUBRAMANIAM GANASAN, Jaya, Prakash ,  RAMIREZ, Cesar, Aaron

IPC: G06F12/0815 ,  G06F9/52 ,  G06F12/0831

CPC classification number: G06F12/0831 ,  G06F9/524 ,  G06F12/0815 ,  G06F12/0833 ,  G06F13/16 ,  G06F13/4027 ,  G06F13/42 ,  G06F2212/1008 ,  G06F2212/621

Abstract: Aspects disclosed herein include avoiding deadlocks in processor-based systems employing retry and in-order-response non-retry bus coherency protocols. In this regard, an interface bridge circuit is communicatively coupled to a first core device that implements a retry bus coherency protocol, and a second core device that implements an in-order-response non-retry bus coherency protocol. The interface bridge circuit receives a snoop command from the first core device, and forwards the snoop command to the second core device. While the snoop command is pending, the interface bridge circuit detects a potential deadlock condition between the first core device and the second core device. In response to detecting the potential deadlock condition, the interface bridge circuit is configured to send a retry response to the first core device. This enables the first core device to continue processing, thereby eliminating the potential deadlock condition.

Abstract translation: 本文公开的方面包括在采用重试和有序响应非重试总线一致性协议的基于处理器的系统中避免死锁。 在这方面，接口桥电路通信地耦合到实现重试总线一致性协议的第一核心设备，以及实现按顺序响应非重试总线一致性协议的第二核心设备。 接口桥电路从第一核心设备接收窥探命令，并将侦听命令转发给第二核心设备。 当snoop命令待处理时，接口桥电路检测第一核心设备和第二核心设备之间的潜在死锁状态。 响应于检测到潜在的死锁状态，接口桥电路被配置为向第一核心设备发送重试响应。 这使得第一核心设备能够继续处理，从而消除潜在的死锁状况。

公开(公告)号：WO2022129992A1

公开(公告)日：2022-06-23

申请号：PCT/IB2020/062033

申请日：2020-12-16

Applicant: COUPANG CORP.

Inventor： KIM, Seokhyun ,  HUANG, Yixiang

IPC: G06F12/0815 ,  G06F12/0813 ,  G06F12/0873

Abstract: A computer-implemented method for synchronizing local caches is disclosed. The method may include receiving a content update which is an update to a data entry stored in local caches of each of a plurality of remote servers. The method may include transmitting the content update to a first remote server to update a corresponding data entry in a local cache of the first remote server. Further, the method may include generating an invalidation command, indicating the change in the corresponding data entry. The method may include transmitting the invalidation command from the first remote server to the message server. The method may include generating, by the message server, a plurality of partitions based on the received invalidation command. The method may include transmitting, from the message server to each of the remote servers, the plurality of partitions, so that the remote servers update their respective local caches.

公开(公告)号：WO2022066222A1

公开(公告)日：2022-03-31

申请号：PCT/US2021/029333

申请日：2021-04-27

Applicant: EMC IP HOLDING COMPANY LLC

Inventor： SOUKHMAN, Alex ,  SHABI, Uri ,  DAVID, Bar

IPC: G06F12/0815 ,  G06F12/0837 ,  G06F12/0893

Abstract: Techniques for caching may include: determining an update to a first data page of a first cache on a first node, wherein a second node includes a second cache and wherein the second cache includes a copy of the first data page; determining, in accordance with one or more criteria, whether to send the update from the first node to the second node; responsive to determining, in accordance with the one or more criteria, to send the update, sending the update from the first node to the second node; and responsive to determining not to send the update, sending an invalidate request from the first node to the second node, wherein the invalidate request instructs the second node to invalidate the copy of the first data page stored in the second cache of the second node.