公开(公告)号：WO2022046304A1

公开(公告)日：2022-03-03

申请号：PCT/US2021/041477

申请日：2021-07-13

Applicant: MICRON TECHNOLOGY, INC

Inventor： LU, Yang ,  STODDARD, Christopher Heaton

IPC: G11C7/22 ,  G11C7/10 ,  H03L7/081 ,  G06F3/06

Abstract: A memory system (10) is provided. The memory system (10) includes a memory system (22) and a data bus (24) electrically coupled to the memory system (22). The memory system (10) further includes one or more memory devices (12, 14, 16) communicatively coupled to the memory system (22) via the data bus (24), wherein each of the one or more memory devices (12, 14, 16) comprises a read training setting configured to adjust a read output timing of data being sent to the memory system (22) during read operations from the one or more memory devices (12, 14, 16).

公开(公告)号：WO2023009963A1

公开(公告)日：2023-02-02

申请号：PCT/US2022/073994

申请日：2022-07-21

Applicant: MICRON TECHNOLOGY, INC.

Inventor： LU, Yang ,  KIM, Kang-Yong

IPC: G06F3/06 ,  G06F13/14

Abstract: Methods, systems, and devices for selective access for grouped memory dies are described. A memory device may be configured with a select die access protocol for a group of memory dies that share a same channel. The protocol may be enabled by one or more commands from the host device, which may be communicated to each of the memory dies of the group via the channel. The command(s) may indicate a first set of one or more memory dies of the group for which a set of commands may be enabled and may also indicate a second set of one or more memory dies of the group for which at least a subset of the set of commands is disabled. When the select die access mode is enabled, the disabled memory dies may be restricted from performing the subset of commands received via the channel.

公开(公告)号：WO2022240896A1

公开(公告)日：2022-11-17

申请号：PCT/US2022/028617

申请日：2022-05-10

Applicant: MICRON TECHNOLOGY, INC.

Inventor： LU, Yang ,  ZHOU, Zhenming ,  ZHU, Jiangli ,  XIE, Tingjun

IPC: G11C7/22 ,  H03K5/156 ,  G06F3/06 ,  G11C2029/4402 ,  G11C2207/2254 ,  G11C29/023 ,  G11C29/028 ,  G11C29/12005 ,  G11C29/12015 ,  G11C29/14 ,  G11C29/44 ,  G11C7/222 ,  G11C8/18

Abstract: A system and method for optimizing a memory sub-system to compensate for memory device degradation. An example system including a memory controller operatively coupled with a memory device and configured to perform operations comprising: updating a setting of the memory device, wherein the setting changes a duty cycle of a signal of the memory device and comprises a first value for a first configuration and comprises a second value for a second configuration; storing error data that indicates errors when using the first configuration and errors when using the second configuration; determining a value for the setting based on the error data, wherein the determined value minimizes errors associated with the memory device; and storing the determined value for the setting of the memory device.

公开(公告)号：WO2022241044A1

公开(公告)日：2022-11-17

申请号：PCT/US2022/028847

申请日：2022-05-11

Applicant: MICRON TECHNOLOGY, INC.

Inventor： ZHOU, Zhenming ,  LU, Yang ,  ZHU, Jiangli ,  XIE, Tingjun

IPC: G11C29/50 ,  G11C29/02 ,  G11C29/023 ,  G11C29/028 ,  G11C29/38 ,  G11C29/44 ,  G11C29/50012

Abstract: A system and method for measuring the degradation of one or more memory devices of a memory sub-system. An example system including a memory controller operatively coupled with a memory device and configured to perform operations comprising: testing different values for a setting of the memory device, wherein the setting of the memory device affects a duty cycle of a signal internal to the memory device; selecting an optimum value for the setting based on access errors during the testing, wherein the optimum value minimizes access errors; determining a degradation measurement for the memory device based on the optimum value; and providing a notification to a host system based on the degradation measurement.

公开(公告)号：WO2023019161A1

公开(公告)日：2023-02-16

申请号：PCT/US2022/074748

申请日：2022-08-10

Applicant: MICRON TECHNOLOGY, INC.

Inventor： LEE, Hyunyoo ,  KIM, Kang-Yong ,  LU, Yang

IPC: G06F3/06

Abstract: Methods, systems, and devices for die location detection for grouped memory dies are described. A memory device may include multiple memory die that are coupled with a shared bus. In some examples, each memory die may include a circuit configured to output an identifier associated with a location of the respective memory die. For example, a first memory die may output a first identifier, based on receiving one or more signals, that identifies a location of the first memory die. Identifying the locations of the respective memory dies may allow for the dies to be individually accessed despite being coupled with a shared bus.