公开(公告)号：WO2023082548A1

公开(公告)日：2023-05-19

申请号：PCT/CN2022/088090

申请日：2022-04-21

Applicant: 长鑫存储技术有限公司

Inventor： 池性洙

IPC: G11C11/4091 ,  G11C8/14 ,  G11C7/18

Abstract: 本公开涉及半导体电路设计领域，涉及一种读出电路的版图结构和数据读出方法，包括：具有相同构造的第一读出电路结构和第二读出电路结构，第一读出电路结构和第二读出电路结构均包括：第一隔离模块，用于根据第一隔离信号导通，电连接位线和第一读出位线，电连接互补位线和第一互补读出位线；第二隔离模块，用于根据第二隔离信号导通，电连接第一读出位线和第二读出位线，电连接第一互补读出位线和第二互补读出位线；感测放大模块，用于第一隔离模块和第二隔离模块导通时，感测并读出存储阵列的数据信号；偏移消除模块，用于根据偏移消除信号，电连接第一互补读出位线与第二读出位线，以提高数据读出的准确性。

公开(公告)号：WO2022124993A1

公开(公告)日：2022-06-16

申请号：PCT/SG2021/050778

申请日：2021-12-10

Applicant: NATIONAL UNIVERSITY OF SINGAPORE [SG]/[SG]

Inventor： VELURI, Hasita ,  THEAN, Voon Yew Aaron ,  LI, Yida ,  TANG, Baoshan

IPC: G06N3/04 ,  G06N3/067 ,  G11C7/18 ,  G11C8/14

Abstract: A memory device for deep neural network, DNN, accelerators, a method of fabricating a memory device for deep neural network, DNN, accelerators, a method of convoluting a kernel [A] with an input feature map [B] in a memory device for a deep neural network, DNN, accelerator, a memory device for a deep neural network, DNN, accelerator, and a deep neural network, DNN, accelerator. The method of fabricating a memory device for deep neural network, DNN, accelerators comprises the steps of forming a first electrode layer comprising a plurality of bit-lines; forming a second electrode layer comprising a plurality of word-lines; and forming an array of memory elements disposed at respective cross-points between the plurality of word-lines and the plurality of bit-lines; wherein at least a portion of the bit-lines are staggered such that a location of a first cross-point between the bit-line and a first word-line is displaced along a direction of the word-lines compared to the cross-point between said bit-line and a second word-line adjacent the first word-line;.or wherein at least a portion of the word-lines are staggered such that a location of a cross-point between the word-line and a first bit-line is displaced along a direction of the bit-lines compared to a cross-point between said word-line and a second bit-line adjacent the first bit-line.

公开(公告)号：WO2022040028A1

公开(公告)日：2022-02-24

申请号：PCT/US2021/045859

申请日：2021-08-13

Applicant: MICRON TECHNOLOGY, INC.

Inventor： VIMERCATI, Daniele

IPC: G11C11/22 ,  H01L27/11597 ,  H01L27/11592 ,  H01L27/11587 ,  H01L27/11595 ,  G11C8/14 ,  G11C7/18

Abstract: Apparatuses, systems, and methods for ferroelectric memory (FeRAM) cell operation. An FeRAM cell may have different charge regions it can operate across. Some regions, such as dielectric regions, may operate faster, but with reduced signal on a coupled digit line. To improve the performance while maintaining increased speed, two digit lines may be coupled to the same sense amplifier, so that the FeRAM cells coupled to both digit lines contribute signal to the sense amplifier. For example a first digit line in a first deck of the memory and a second digit line in a second deck of the memory may both be coupled to the sense amplifier. In some embodiments, additional digit lines may be used as shields (e.g., by coupling the shield digit lines to a ground voltage) to further improve the signal-to-noise ratio.

公开(公告)号：WO2022036540A1

公开(公告)日：2022-02-24

申请号：PCT/CN2020/109723

申请日：2020-08-18

Applicant: YANGTZE ADVANCED MEMORY INDUSTRIAL INNOVATION CENTER CO., LTD

Inventor： LIU, Jun

IPC: G11C7/12 ,  G11C7/18 ,  G11C8/08 ,  G11C8/14

Abstract: A three-dimensional memory including bit line contacts arranged in two portions, a first portion of bit line contacts coupled to the bit lines at positions proximate a first edge of the array of memory cells and a second portion of bit line contacts coupled to the bit lines at positions proximate a second edge of the array of memory cells; and word line contacts arranged in two portions, a first portion of word line contacts coupled to the word lines at positions proximate a third edge of the array of memory cells and a second portion of word line contacts coupled to the word lines at positions proximate a fourth edge of the array of memory cells.

公开(公告)号：WO2020142743A1

公开(公告)日：2020-07-09

申请号：PCT/US2020/012261

申请日：2020-01-03

Applicant: SYNOPSYS, INC.

Inventor： SIDDIQUI, M. Sultan, M. ,  SHARMA, Sudhir, Kumar ,  PORWAL, Saurabh ,  PANNALAL, Khatik, Bhagvan ,  KUMAR, Sudhir

IPC: G11C7/12 ,  G11C7/18 ,  G11C11/412 ,  G11C11/413 ,  H01L27/11

Abstract: A structure for an integrated circuit is disclosed for storing data. The integrated circuit includes a memory cell array of bit cells configured in a static random access memory (SRAM) architecture. The memory cell array is coupled to wordlines arranged in rows that control operations such as Read and Write operations. To enhance the read sensing margin of the SRAM configuration, the read port of a bit cell may include a wordline that drives two transistors (e.g., a PMOS and an NMOS transistor) to reduce data-dependent current leakage from a read bitline. An additional weak transistor keeper configuration may be used in the integrated circuit to compensate for current leakage from the read bitline. For example, a weak NMOS keeper that includes a sense amplifier, an inverter, and an NMOS connected to supply voltage VDD provides a path between the read bitline and VDD through the weak NMOS keeper.

公开(公告)号：WO2019055182A1

公开(公告)日：2019-03-21

申请号：PCT/US2018/047438

申请日：2018-08-22

Applicant: SILICON STORAGE TECHNOLOGY, INC.

Inventor： TIWARI, Vipin ,  DO, Nhan

IPC: H01L27/02 ,  H01L27/04 ,  H01L27/07 ,  H01L27/11507 ,  H01L27/11517 ,  H01L29/02 ,  G11C7/18

Abstract: A memory array with memory cells arranged in rows and columns. Each memory cell includes source and drain regions with a channel region there between, a floating gate disposed over a first channel region portion, and a second gate disposed over a second channel region portion. A plurality of bit lines each extends along one of the columns and is electrically connected to the drain regions of a first group of one or more of the memory cells in the column and is electrically isolated from the drain regions of a second group of one or more of the memory cells in the column. A plurality of source lines each is electrically connected to the source regions memory cells in one of the columns or rows. A plurality of gate lines each is electrically connected to the second gates of memory cells in one of the columns or rows.

公开(公告)号：WO2018193699A1

公开(公告)日：2018-10-25

申请号：PCT/JP2018/005541

申请日：2018-02-16

Applicant: 株式会社ソシオネクスト

Inventor： 山上　由展

IPC: G11C11/419 ,  G11C7/12 ,  G11C7/18

Abstract: 導体記憶回路（Ａ）は、第１のローカルリードビット線に接続された複数の第１のメモリセル（ＭＣ）および第１のプリチャージトランジスタ（Ｐ１１）と、第２のローカルリードビット線に接続された複数の第２のメモリセル（ＭＣ）および第２のプリチャージトランジスタ（Ｐ１２）とを有する。そして、第１のおよび第２のローカルリードビット線に出力される信号に応じた信号がゲート回路および出力回路を経由してグローバルリードビット線に出力される。第１および第２のローカルリードビット線の間には、ゲートがゲート回路の出力に接続された第１のトランジスタ（Ｐ３１，Ｐ３２）が設けられている。

公开(公告)号：WO2017208016A1

公开(公告)日：2017-12-07

申请号：PCT/GB2017/051593

申请日：2017-06-02

Applicant: SURECORE LIMITED

Inventor： COSEMANS, Stefan ,  ROOSELEER, Bram

IPC: G11C11/419 ,  G11C7/18 ,  G11C7/12 ,  G11C5/14 ,  G11C8/12 ,  G11C8/10 ,  G11C11/418

CPC classification number: G11C11/419 ,  G11C5/145 ,  G11C7/12 ,  G11C7/18 ,  G11C8/10 ,  G11C8/12 ,  G11C11/418 ,  G11C2207/005

Abstract: There is provided a method for accessing a memory cell of a plurality of memory cells that are part of a memory unit, the memory cells being grouped into a plurality of memory cell groups, wherein each memory cell group is associated with one or more local bit lines with each of the one or more local bit lines being operatively connected to a corresponding global bit line via a passgate comprising a PMOS transistor. The method comprises connecting each of the one or more local bit lines to the corresponding global bit line by decreasing a gate voltage that is applied to a gate of the corresponding PMOS transistor to a value that is sufficient to allow the PMOS transistor to conduct, wherein the value of the gate voltage that is sufficient to allow the PMOS transistor to conduct is either a positive or negative voltage.

Abstract translation: 提供了一种用于访问作为存储器单元的一部分的多个存储器单元的存储器单元的方法，所述存储器单元被分组为多个存储器单元组，其中每个存储器单元组 与一个或多个局部位线相关联，所述一个或多个局部位线中的每一个经由包括PMOS晶体管的传输门可操作地连接到对应的全局位线。 该方法包括通过将施加到对应的PMOS晶体管的栅极的栅极电压减小到足以允许PMOS晶体管导通的值来将一个或多个局部位线中的每一个连接到对应的全局位线，其中 足以使PMOS晶体管导通的栅极电压的值是正电压或负电压。

公开(公告)号：WO2017163208A1

公开(公告)日：2017-09-28

申请号：PCT/IB2017/051680

申请日：2017-03-23

Applicant: GSI TECHNOLOGY INC.

Inventor： AKERIB, Avidan ,  LASSERRE, Pat

IPC: G11C15/04 ,  G06F9/30 ,  G11C7/00 ,  G11C7/10 ,  G11C7/18 ,  G11C8/10 ,  G11C15/00

CPC classification number: G06F17/16 ,  G06F3/0604 ,  G06F3/0644 ,  G06F3/0659 ,  G06F3/067 ,  G06N3/04 ,  G06N3/063 ,  G06N3/08 ,  G11C7/1006 ,  G11C7/22 ,  G11C8/10 ,  G11C15/00

Abstract: A method for an associative memory array includes storing each column of a matrix in an associated column of the associative memory array, where each bit in row j of the matrix is stored in row R-matrix-row-j of the array, storing a vector in each associated column, where a bit j from the vector is stored in an R-vector-bit-j row of the array. The method includes simultaneously activating a vector-matrix pair of rows R- vector-bit-j and R-matrix-row-j to concurrently receive a result of a Boolean function on all associated columns, using the results to calculate a product between the vector- matrix pair of rows, and writing the product to an R-product-j row in the array.

Abstract translation: 用于关联存储器阵列的方法包括将矩阵的每列存储在关联存储器阵列的关联列中，其中矩阵的行j中的每个位存储在行R矩阵行 -j，将矢量存储在每个相关列中，其中来自矢量的位j存储在该阵列的R矢量位j行中。 该方法包括同时激活行R向量位j和R矩阵行j的向量矩阵对以同时接收所有相关列上的布尔函数的结果，使用结果来计算 向量矩阵行对，并将产品写入数组中的R-product-j行。

公开(公告)号：WO2017149295A1

公开(公告)日：2017-09-08

申请号：PCT/GB2017/050540

申请日：2017-02-28

Applicant: SURECORE LIMITED

Inventor： COSEMANS, Stefan ,  ROOSELEER, Bram

IPC: G11C11/419 ,  G11C7/06 ,  G11C7/08 ,  G11C7/12 ,  G11C7/10 ,  G11C8/16 ,  G11C7/22 ,  G11C7/18

Abstract: There is provided a multiple data rate memory configured to implement first and second memory accesses within a single cycle of an external clock signal. The memory comprises a plurality of memory cell groups, each memory cell group comprising a plurality of memory cells that are each operatively connected to at least one local bit line, the at least one local bit line of each memory cell group being connected to a local-to-global interface circuit. The local-to- global interface circuit is configured to control the state of at least one first global bit line in dependence upon the state of the at least one local bit line during the first memory access and to control the state of at least one second global bitline in dependence upon the state of the at least one local bit line during the second memory access.

Abstract translation: 提供了一种多数据速率存储器，其被配置为在外部时钟信号的单个周期内实现第一和第二存储器访问。 存储器包括多个存储单元组，每个存储单元组包括多个存储单元，每个存储单元可操作地连接到至少一个本地位线，每个存储单元组的至少一个本地位线连接到本地 全球接口电路。 局部到全局接口电路被配置成根据第一存储器访问期间至少一条局部位线的状态来控制至少一条第一全局位线的状态，并控制至少一条第二全局位线的状态 全局位线取决于在第二次存储器访问期间至少一条局部位线的状态。