公开(公告)号：WO2022132225A1

公开(公告)日：2022-06-23

申请号：PCT/US2021/036868

申请日：2021-06-10

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： TIRUKKONDA, Roshan ,  SAID, Ramy Nashed Bassely ,  KANAKAMEDALA, Senaka ,  SHARANGPANI, Rahul ,  MAKALA, Raghuveer S. ,  RAJASHEKHAR, Adarsh ,  ZHOU, Fei

IPC: H01L27/11597 ,  H01L27/1159 ,  H01L27/11595 ,  H01L27/11587

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers and memory stack structures vertically extending through the alternating stack. Each of the memory stack structures includes a vertical semiconductor channel and a vertical stack of ferroelectric memory elements surrounding the vertical semiconductor channel and located at levels of the electrically conductive layers. Each of the ferroelectric memory elements includes a respective vertical stack of a first ferroelectric material portion and a second ferroelectric material portion that differs from the first ferroelectric material portion by at least one of a material composition and a lateral thickness.

公开(公告)号：WO2022231662A1

公开(公告)日：2022-11-03

申请号：PCT/US2021/065564

申请日：2021-12-29

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： SAID, Ramy Nashed Bassely ,  MAKALA, Raghuveer S. ,  KANAKAMEDALA, Senaka ,  SHARANGPANI, Rahul

IPC: H01L27/11587 ,  H01L27/1159 ,  H01L27/11597 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11548 ,  H01L27/11565 ,  H01L27/11575 ,  H01L27/11582 ,  H01L21/28 ,  H01L29/792

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, memory openings extending through the alternating stack, and memory opening fill structures located in the memory openings and containing a respective vertical semiconductor channel and a respective memory film. Each of the electrically conductive layers includes a tubular metallic liner in contact with a respective outer sidewall segment of a respective one of the memory opening fill structures, an electrically conductive barrier layer contacting the respective tubular metallic liner and two of the insulating layers, and a metallic fill material layer contacting the electrically conductive barrier layer, and not contacting the tubular metallic liner or any of the insulating layers. The memory opening fill structures are formed after performing a halogen outgassing anneal through the memory openings to reduce or eliminate the halogen outgassing damage in the layers of the memory film.

公开(公告)号：WO2021141612A1

公开(公告)日：2021-07-15

申请号：PCT/US2020/034798

申请日：2020-05-28

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： ZHANG, Yanli ,  ALSMEIER, Johann ,  ZHOU, Fei

IPC: G11C11/40 ,  H01L21/8238 ,  H01L29/78 ,  G11C11/223 ,  H01L27/11587 ,  H01L27/11597 ,  H01L29/6684 ,  H01L29/78391

Abstract: A semiconductor structure includes layer stack structures laterally extending along a first horizontal direction and spaced apart from each other along a second horizontal direction by line trenches. Each of the layer stack structures includes at least one instance of a unit layer sequence that includes, from bottom to top or top to bottom, a doped semiconductor source strip, a channel-level insulating strip, and a doped semiconductor drain strip. Line trench fill structures are located within a respective one of the line trenches. Each of the line trench fill structures includes a laterally-alternating sequence of memory pillar structures and dielectric pillar structures. Each of the memory pillar structures includes a gate electrode, at least one pair of ferroelectric dielectric layers, and at least one pair of vertical semiconductor channels located at each level of the channel-level insulating strips.

公开(公告)号：WO2021029915A1

公开(公告)日：2021-02-18

申请号：PCT/US2020/023423

申请日：2020-03-18

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： SHARANGPANI, Rahul ,  RAJASHEKHAR, Adarsh ,  MAKALA, Raghuveer S. ,  ZHANG, Yanli ,  YANG, Seung-Yeul ,  ZHOU, Fei

IPC: H01L27/11597 ,  H01L27/11587 ,  H01L27/1159 ,  H01L21/02

Abstract: A ferroelectric memory device includes a semiconductor channel, a gate electrode, and a ferroelectric memory element located between the semiconductor channel and the gate electrode. The ferroelectric memory element includes at least one ferroelectric material portion and at least one antiferroelectric material portion.

公开(公告)号：WO2020086566A1

公开(公告)日：2020-04-30

申请号：PCT/US2019/057418

申请日：2019-10-22

Applicant: LAM RESEARCH CORPORATION

Inventor： LILL, Thorsten ,  SHEN, Meihua ,  HOANG, John ,  WU, Hui-Jung ,  GUNAWAN, Gereng ,  PAN, Yang

IPC: H01L27/11582 ,  H01L27/11597 ,  H01L27/11565 ,  H01L27/06 ,  H01L29/792 ,  H01L29/66 ,  H01L27/11587 ,  H01L27/108

Abstract: A three-dimensional (3D) memory structure includes memory cells and a plurality of oxide layers and a plurality of word line layers. The plurality of oxide layers and the plurality of word line layers are alternately stacked in a first direction. A plurality of double channel holes extend through the plurality of oxide layers and the plurality of word line layers in the first direction. The plurality of double channel holes have a peanut-shaped cross-section in a second direction that is transverse to the first direction.

公开(公告)号：WO2022154827A1

公开(公告)日：2022-07-21

申请号：PCT/US2021/036870

申请日：2021-06-10

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： SHARANGPANI, Rahul ,  MAKALA, Raghuveer S. ,  ZHOU, Fei ,  RAJASHEKHAR, Adarsh

IPC: H01L27/11597 ,  H01L27/1159 ,  H01L27/11587 ,  H01L29/66 ,  H01L29/78

Abstract: A ferroelectric memory device includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and containing a vertical stack of memory elements and a vertical semiconductor channel. Each memory element within the vertical stack of memory elements includes a crystalline ferroelectric memory material portion and an epitaxial template portion.

公开(公告)号：WO2022132540A1

公开(公告)日：2022-06-23

申请号：PCT/US2021/062495

申请日：2021-12-08

Applicant: SYNOPSYS, INC.

Inventor： HORCH, Andrew Edward

IPC: H01L27/112 ,  H01L27/11587

Abstract: A one-transistor (1T) one-time programmable (OTP) anti-fuse bitcell is provided. The 1T OTP anti-fuse bitcell includes a gate, a diffusion region including at least two sub-regions, and a gate oxide region located between the gate and the diffusion region, the gate oxide region including a thin gate oxide region and a thick gate oxide region.

公开(公告)号：WO2022040028A1

公开(公告)日：2022-02-24

申请号：PCT/US2021/045859

申请日：2021-08-13

Applicant: MICRON TECHNOLOGY, INC.

Inventor： VIMERCATI, Daniele

IPC: G11C11/22 ,  H01L27/11597 ,  H01L27/11592 ,  H01L27/11587 ,  H01L27/11595 ,  G11C8/14 ,  G11C7/18

Abstract: Apparatuses, systems, and methods for ferroelectric memory (FeRAM) cell operation. An FeRAM cell may have different charge regions it can operate across. Some regions, such as dielectric regions, may operate faster, but with reduced signal on a coupled digit line. To improve the performance while maintaining increased speed, two digit lines may be coupled to the same sense amplifier, so that the FeRAM cells coupled to both digit lines contribute signal to the sense amplifier. For example a first digit line in a first deck of the memory and a second digit line in a second deck of the memory may both be coupled to the sense amplifier. In some embodiments, additional digit lines may be used as shields (e.g., by coupling the shield digit lines to a ground voltage) to further improve the signal-to-noise ratio.

公开(公告)号：WO2022031349A1

公开(公告)日：2022-02-10

申请号：PCT/US2021/034643

申请日：2021-05-27

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： CUI, Zhixin ,  CHIBVONGODZE, Hardwell ,  GAUTAM, Rajdeep

IPC: G11C16/10 ,  G11C11/22 ,  G11C16/04 ,  G11C16/26 ,  G11C17/16 ,  G11C17/18 ,  H01L23/522 ,  G11C11/005 ,  G11C11/223 ,  G11C11/2273 ,  G11C11/2275 ,  G11C16/0408 ,  G11C16/0466 ,  G11C2216/26 ,  H01L23/5226 ,  H01L27/11206 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11582 ,  H01L27/11587 ,  H01L27/1159 ,  H01L27/11597

Abstract: First alternating stacks of first insulating strips and first spacer material strips is formed in a first device region, second alternating stacks of second insulating strips and second spacer material strips are formed in a second device region. Each of the first line trenches is filled with a respective laterally alternating sequence of memory stack structures and first dielectric pillar structures to form a three-dimensional NAND memory. Each of the memory stack structures includes a vertical semiconductor channel and a vertical stack of memory elements. Each of the second line trenches with a respective laterally alternating sequence of active region assemblies of lateral field effect transistors and second dielectric pillar structures to form a three-dimensional NOR memory. Each of the active region assemblies includes a source pillar, a drain pillar, and a tubular channel region. The spacer material strips include, or are subsequently replaced with, electrically conductive strips.

公开(公告)号：WO2022000486A1

公开(公告)日：2022-01-06

申请号：PCT/CN2020/100210

申请日：2020-07-03

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： TANG, Qiang

IPC: G11C11/22 ,  G11C11/221 ,  G11C11/223 ,  G11C11/225 ,  G11C11/2255 ,  G11C11/2257 ,  G11C11/2259 ,  G11C11/2273 ,  G11C11/2275 ,  G11C11/40 ,  G11C2213/71 ,  G11C5/02 ,  H01L27/11587 ,  H01L27/1159 ,  H01L27/11597

Abstract: A programming method for a three-dimensional ferroelectric memory device is disclosed. The programming method includes applying a first voltage on a selected word line of a target memory cell. The target memory cell has a first logic state and a second logic state corresponding to a first threshold voltage and a second threshold voltage, respectively. The first and second threshold voltages are determined by two opposite electric polarization directions of a ferroelectric film in the target memory cell. The programming method also includes applying a second voltage on a selected bit line, where a voltage difference between the first and second voltages has a magnitude larger than a coercive voltage of the ferroelectric film such that the target memory cell is switched from the first logic state to the second logic state.