公开(公告)号：WO2013095477A1

公开(公告)日：2013-06-27

申请号：PCT/US2011/066683

申请日：2011-12-22

Applicant: INTEL CORPORATION ,  YIGZAW, Theodros ,  SANTHANAKRISHNAN, Geeyarpuram N. ,  SRINIVASA, Ganapati N. ,  VARGAS, Jose A. ,  SHAFI, Hisham ,  MISHAELI, Michael ,  COHEN, Ehud ,  SPERBER, Zeev ,  RAIKIN, Shlomo ,  KUMAR, Mohan J. ,  MANDELBLAT, Julius Y.

Inventor： YIGZAW, Theodros ,  SANTHANAKRISHNAN, Geeyarpuram N. ,  SRINIVASA, Ganapati N. ,  VARGAS, Jose A. ,  SHAFI, Hisham ,  MISHAELI, Michael ,  COHEN, Ehud ,  SPERBER, Zeev ,  RAIKIN, Shlomo ,  KUMAR, Mohan J. ,  MANDELBLAT, Julius Y.

IPC: G06F11/08 ,  G06F11/10

CPC classification number: G06F11/1405 ,  G06F11/1064

Abstract: An apparatus and method are described for detecting and correcting data fetch errors within a processor core. For example, one embodiment of an instruction processing apparatus for detecting and recovering from data fetch errors comprises: at least one processor core having a plurality of instruction processing stages including a data fetch stage and a retirement stage; and error processing logic in communication with the processing stages to perform the operations of: detecting an error associated with data in response to a data fetch operation performed by the data fetch stage; and responsively performing one or more operations to ensure that the error does not corrupt an architectural state of the processor core within the retirement stage.

Abstract translation: 描述了用于检测和校正处理器核心内的数据获取错误的装置和方法。 例如，用于检测和从数据获取错误中恢复的指令处理装置的一个实施例包括：具有多个指令处理阶段的至少一个处理器核心，包括数据获取阶段和退休阶段; 以及与处理级通信的错误处理逻辑，以执行以下操作：响应于由数据获取级执行的数据获取操作，检测与数据相关联的错误; 并且响应地执行一个或多个操作以确保错误不会在退休阶段内破坏处理器核心的体系结构状态。

公开(公告)号：WO2013095437A1

公开(公告)日：2013-06-27

申请号：PCT/US2011/066492

申请日：2011-12-21

Applicant: INTEL CORPORATION ,  NACHIMUTHU, Murugasamy K. ,  KUMAR, Mohan

Inventor： NACHIMUTHU, Murugasamy K. ,  KUMAR, Mohan

IPC: G06F12/02 ,  G06F12/08 ,  G11C13/02

CPC classification number: G11C14/009 ,  G06F9/30047 ,  G06F12/0804 ,  G06F12/0868 ,  G06F12/0891 ,  G06F2212/1016 ,  G06F2212/1044 ,  G11C13/0004

Abstract: A system and method are described for intelligently flushing data from a processor cache. For example, a system according to one embodiment of the invention comprises: a processor having a cache from which data is flushed, the data associated with a particular system address range; and a PCM memory controller for managing access to data stored in a PCM memory device corresponding to the particular system address range; the processor determining whether memory flush hints are enabled for the specified system address range, wherein if memory flush hints are enabled for the specified system address range then the processor sending a memory flush hint to a PCM memory controller of the PCM memory device and wherein the PCM memory controller uses the memory flush hint to determine whether to save the flushed data to the PCM memory device.

Abstract translation: 描述了用于从处理器高速缓存中智能地刷新数据的系统和方法。 例如，根据本发明的一个实施例的系统包括：处理器，其具有从其中刷新数据的高速缓存，与特定系统地址范围相关联的数据; 以及PCM存储器控制器，用于管理存储在对应于所述特定系统地址范围的PCM存储器设备中的数据的访问; 所述处理器确定是否对所述指定的系统地址范围启用了存储器刷新提示，其中如果为所述指定的系统地址范围启用了存储器刷新提示，则所述处理器向PCM存储器件的PCM存储器控制器发送存储器刷新提示， PCM存储器控制器使用内存刷新提示来确定是否将已刷新的数据保存到PCM存储器设备。

公开(公告)号：WO2013095404A1

公开(公告)日：2013-06-27

申请号：PCT/US2011/066302

申请日：2011-12-20

Applicant: INTEL CORPORATION ,  RAMANUJAN, Raj K. ,  HINTON, Glenn J. ,  ZIMMERMAN, David J.

Inventor： RAMANUJAN, Raj K. ,  HINTON, Glenn J. ,  ZIMMERMAN, David J.

IPC: G06F12/08

CPC classification number: G06F12/0891 ,  G06F1/3225 ,  G06F1/3275 ,  G06F12/0804 ,  G06F12/0864 ,  G06F12/0868 ,  G06F12/0873 ,  G06F12/0895 ,  G06F2212/1028 ,  G06F2212/601 ,  G06F2212/6082 ,  Y02D10/13 ,  Y02D10/14

Abstract: A system and method are described for flushing a specified region of a memory side cache (MSC) within a multi-level memory hierarchy. For example, a computer system according to one embodiment comprises: a memory subsystem comprised of a non-volatile system memory and a volatile memory side cache (MSC) for caching portions of the non-volatile system memory; and a flush engine for flushing a specified region of the MSC to the non-volatile system memory in response to a deactivation condition associated with the specified region of the MSC.

Abstract translation: 描述了用于刷新多级存储器层级内的存储器侧缓存（MSC）的指定区域的系统和方法。 例如，根据一个实施例的计算机系统包括：由非易失性系统存储器和用于高速缓存非易失性系统存储器的部分的易失性存储器侧缓存（MSC）组成的存储器子系统; 以及冲洗引擎，用于响应于与MSC的指定区域相关联的去激活条件，将MSC的指定区域冲入非易失性系统存储器。

公开(公告)号：WO2013095385A1

公开(公告)日：2013-06-27

申请号：PCT/US2011/066179

申请日：2011-12-20

Applicant: INTEL CORPORATION ,  RAMANUJAN, Raj K. ,  SCHMISSEUR, Mark A.

Inventor： RAMANUJAN, Raj K. ,  SCHMISSEUR, Mark A.

IPC: G11C13/02 ,  G06F12/00

CPC classification number: G06F12/0246 ,  G06F12/0866 ,  G06F2212/214 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0061 ,  G11C16/3418 ,  G11C2013/0054 ,  G11C2013/0057

Abstract: A system and method are described for selecting a demarcation voltage for read and write operations. Embodiments of the invention provide a scheme to use multiple VDMs to cover the case where power-on drift is different from power-off drift of the PCMS cells. The controller automatically manages this through tracking refreshes and writes. In addition, the embodiments of the invention provide an efficient scheme to reduce the performance impact of the penalty box following a write by tracking recent write addresses through a hash-table or similar scheme. By way of example, a method in accordance with one embodiment comprises: detecting a read operation directed to a first block of a PCMS memory; determining whether a write operation has previously occurred to the first block within a specified amount of time prior to the read operation; using a first demarcation voltage (VDM) for the read operation if the write operation has previously occurred to the first block within the specified amount of time prior to the write operation; and using a second VDM for the read operation if the write operation has not previously occurred to the first block within the specified amount of time prior to the write or refresh operation.

Abstract translation: 描述了用于选择用于读取和写入操作的分界电压的系统和方法。 本发明的实施例提供了使用多个VDM来覆盖上电漂移与PCMS单元的断电漂移不同的情况的方案。 控制器通过跟踪刷新和写入自动进行管理。 此外，本发明的实施例提供了一种有效的方案，以通过通过散列表或类似方案跟踪最近的写入地址来减少写入之后的惩罚盒的性能影响。 作为示例，根据一个实施例的方法包括：检测针对PCMS存储器的第一块的读取操作; 在所述读取操作之前的指定时间内确定是否先前对所述第一块发生了写入操作; 如果在写操作之前的指定时间内先前已经对第一块发生写操作，则使用第一分界电压（VDM）作为读操作; 以及如果在所述写入或刷新操作之前的所述指定时间量内的所述第一块以前没有发生写入操作，则使用第二VDM进行所述读取​​操作。

公开(公告)号：WO2007005819A1

公开(公告)日：2007-01-11

申请号：PCT/US2006/025960

申请日：2006-06-29

Applicant: INTEL CORPORATION ,  GROBMAN, Steven, L. ,  KINNEY, Michael, D.

Inventor： GROBMAN, Steven, L. ,  KINNEY, Michael, D.

IPC: G06F9/46

CPC classification number: G06F9/461

Abstract: In some embodiments, the invention involves saving limited context information when transitioning between virtual machines. A predetermined set of instructions and events cause a trap. A bit or flag is set to indicate that the event has occurred within a virtual machine. The virtual machine monitor determines whether specific register sets must be saved or restored upon a context switch, based on whether the flag has been set. Other embodiments are described and claimed.

Abstract translation: 在一些实施例中，本发明涉及在虚拟机之间转换时保存有限的上下文信息。 一组预定的指令和事件会引起陷阱。 位或标志被设置为指示事件已在虚拟机中发生。 虚拟机监视器根据标志是否被设置，确定在上下文切换时是否必须保存或恢复特定寄存器集。 描述和要求保护其他实施例。