公开(公告)号：WO1996002054A1

公开(公告)日：1996-01-25

申请号：PCT/JP1995001364

申请日：1995-07-07

Applicant: SONY CORPORATION ,  OKAZAKI, Toru ,  YOSHIMURA, Shunji

Inventor： SONY CORPORATION

IPC: G11B20/10

CPC classification number: G11B20/1426 ,  G11B2020/1461 ,  G11B2020/1465 ,  G11B2020/1473 ,  H03M5/14 ,  H03M5/145 ,  H03M7/46 ,  H03M13/31

Abstract: The present invention uses a conversion table a part of which is duplexed in order to directly convert input M-bit data into an N-bit code without using a margin bit. This conversion table comprises first and second sub-tables each including a plurality of code groups, and these code groups contain different codes to the same input data. In the second sub-table, a part of the first sub-table obtaining by allocating different codes to the data ranging from the first input data to the second input data of the sub-table is duplexed. The set of the codes of the duplexed portion of the conversion table is so constituted as to take a digital sum variation of opposite signs, and codes are sequentially allocated to the input data from the code having the greater absolute value of the digital sum variation. In this way, the present invention can appropriately suppress low frequency components of modulation signals.

Abstract translation: 本发明使用其一部分是双工的转换表，以便将输入M位数据直接转换为N位代码而不使用边沿位。 该转换表包括每个包括多个代码组的第一和第二子表，并且这些代码组对相同的输入数据包含不同的代码。 在第二子表中，通过对从子表的第一输入数据到第二输入数据范围的数据分配不同的代码获得第一子表的一部分是双工的。 转换表的双工部分的代码组被构成为获得相反符号的数字和变化，并且代码从具有数字和变化的绝对值较大的代码顺序地分配给输入数据。 以这种方式，本发明可以适当地抑制调制信号的低频分量。

公开(公告)号：WO1995022802A2

公开(公告)日：1995-08-24

申请号：PCT/IB1995000070

申请日：1995-02-01

Applicant: PHILIPS ELECTRONICS N.V. ,  PHILIPS NORDEN AB

Inventor： PHILIPS ELECTRONICS N.V. ,  PHILIPS NORDEN AB ,  SCHOUHAMER IMMINK, Kornelis, Antonie

IPC: G06K00/00

CPC classification number: H03M5/145 ,  G11B20/1426 ,  H04L7/041

Abstract: The Patent Applications relates to a method of converting a series of m-bit information words (1) to a modulated signal (7). For each information word from the series an n-bit code word (4) is delivered. The delivered code words (4) are converted to the modulated signal (7). The code words (4) are distributed over at least one group (G11, G12) of a first type and at least one group (G2) of a second type. For the delivery of each of the code words belonging to the group (G11, G12) of the first type the associated group establishes a coding state (S1, S4) of the first type. When each of the code words (4) belonging to the group (G2) of the second type is delivered, a coding state (S2, S3) of the second type is established which is determined by an information word belonging to the delivered code word. When one of the code words (4) is assigned to the received information word (1), this code word is selected from a set (V1, V2, V3, V4) of code words which depends on the coding states (S1, S2, S3, S4). The sets of code words (V2, V3) belonging to the coding states (S1, S2) of the second type are disjunct. In this coding method the number of unique bit combinations that may be established by the code words in the series are enlarged. The modulated signal (7) thus obtained may be reconverted to information words (4) by first converting the modulated signal (7) to a series of code words (4) and then assigning an information word (1) to each of the code words from the series in dependence on the code word to be converted and also in dependence on the logical values of the bit string bits which are situated at predetermined positions relative to the code word. Furthermore, a recording device and a reading device are disclosed.

Abstract translation: 专利申请涉及将一系列m位信息字（1）转换为调制信号（7）的方法。 对于来自该系列的每个信息字，传送n位码字（4）。 传送的代码字（4）被转换成调制信号（7）。 代码字（4）分布在第一类型的至少一个组（G11，G12）和第二类型的至少一个组（G2）中。 为了输送属于第一类型的组（G11，G12）的每个代码字，相关联的组建立第一类型的编码状态（S1，S4）。 当属于第二类型的组（G2）的每个代码字（4）被传送时，建立第二类型的编码状态（S2，S3），该编码状态由属于所递送代码字的信息字确定 。 当代码字（4）中的一个被分配给所接收的信息字（1）时，从代码字的集合（V1，V2，V3，V4）中选择该码字，该码字取决于编码状态（S1，S2 ，S3，S4）。 属于第二类型的编码状态（S1，S2）的码字集合（V2，V3）是分离的。 在该编码方法中，可以通过该系列中的码字建立的唯一位组合的数量被放大。 这样获得的调制信号（7）可以通过首先将调制信号（7）转换成一系列代码字（4）然后将信息字（1）分配给每个代码字 依赖于要转换的代码字，并且还取决于位于相对于代码字的预定位置的位串位的逻辑值。 此外，公开了一种记录装置和读取装置。

公开(公告)号：WO1995002283A1

公开(公告)日：1995-01-19

申请号：PCT/GB1994001478

申请日：1994-07-07

Applicant: HEWLETT-PACKARD COMPANY ,  JEDWAB, Jonathan ,  CROUCH, Simon, Edwin ,  CUNNINGHAM, David, George

Inventor： HEWLETT-PACKARD COMPANY

IPC: H03M13/00

CPC classification number: H04L25/4908 ,  H03M5/145 ,  H03M13/31 ,  H04L25/14

Abstract: A method of coding, and a coder, using a code in which data words are assigned to code word pairs in a selective manner, so that the value of a data word error resulting from inversion of a bit in a code word may be specific to and dependent solely upon the position within the code word of the inverted bit.

Abstract translation: 一种编码方法和编码器，其中使用代码，其中数据字被选择性地分配给码字对，使得由代码字中的位的反转产生的数据字错误的值可以是特定于 并且仅依赖于反转位的码字内的位置。

公开(公告)号：WO1988006819A1

公开(公告)日：1988-09-07

申请号：PCT/US1988000601

申请日：1988-02-26

Applicant: TELXON CORPORATION

Inventor： TELXON CORPORATION ,  CAMPO, James, A. ,  SUTHERLAND, Jeffrey, W. ,  KRILL, Carl, E., III

IPC: H03K07/08

CPC classification number: H03M5/145 ,  H04L25/4902

Abstract: An encoding and decoding system for electronic data communication system, wherein each character to be transmitted is encoded as a unique multi-bit binary value. The total number of bits as well as the number of logic one bits in all unique multi-bit binary values are the same. A pulse generating means generates a wide pulse for each logic one and a narrow pulse for each logic zero. The pulses which make up a unique pulse form for each data character to be transmitted are of alternating polarity and are transmitted as analog signals.

公开(公告)号：WO2015024062A8

公开(公告)日：2016-02-25

申请号：PCT/AU2014000832

申请日：2014-08-22

Applicant: UNIV SOUTH AUSTRALIA

Inventor： GRANT ALEXANDER JAMES ,  LECHNER GOTTFRIED ,  POLLOK ANDRE ,  MCKILLIAM ROBERT GEORGE ,  LAND INGMAR RUDIGER ,  HALEY DAVID VICTOR LAWRIE ,  LAVENANT MARC PIERRE DENIS

IPC: H03M13/00 ,  G06F11/10

CPC classification number: H04L1/0041 ,  H03M5/145 ,  H03M13/09 ,  H03M13/1102 ,  H03M13/23 ,  H03M13/2957 ,  H03M13/31 ,  H03M13/6325 ,  H03M13/6356 ,  H04L1/00 ,  H04L1/0045 ,  H04L1/0061 ,  H04L1/0071

Abstract: The invention relates to method and apparatus for improving the performance of communication systems using Run Length Limited (RLL) messages such as the existing Automatic Identification System (AlS). A binary data sequence is Forward Error Correction (FEC) coded and then the sequence is compensated, for example by bit-erasure, so that either bit-stuffing is not required, or a bit stuffer will not be activated to ensure that the coded sequence meets the RLL requirement. Various embodiments are described to handle different architectures or input points for the FEC encoder and bit erasure module. The bit erasure module may also add dummy bits to ensure a RLL compliant CRC or to selectively add bits to a reserve buffer to compensate for later bit stuffing in a header. Additional RLL training sequences may also be added to assist in, receiver acquisition.

Abstract translation: 本发明涉及使用诸如现有自动识别系统（AlS）的运行长度有限（RLL）消息来改善通信系统性能的方法和装置。 二进制数据序列是前向纠错（FEC）编码的，然后例如通过比特擦除来补偿序列，使得不需要任何一个比特填充，或者一个填充填充器将不被激活以确保编码序列 符合RLL要求。 描述了各种实施例来处理用于FEC编码器和位擦除模块的不同架构或输入点。 比特擦除模块还可以添加伪比特以确保符合RLL的CRC，或者选择性地将比特添加到保留缓冲器中以补偿头中稍后的比特填充。 还可以添加额外的RLL训练序列以辅助接收器采集。

公开(公告)号：WO2016020280A1

公开(公告)日：2016-02-11

申请号：PCT/EP2015/067654

申请日：2015-07-31

Applicant: THOMSON LICENSING

Inventor： CHEN, Xiaoming ,  BLAWAT, Meinolf ,  GAEDKE, Klaus ,  HUETTER, Ingo

IPC: H03M13/01 ,  H03M13/03 ,  H03M13/05

CPC classification number: G06N3/123 ,  G11C7/1006 ,  G11C13/0019 ,  H03M5/145

Abstract: A code book is generated for mapping source to target code words which allows encoding source data at reduced probability of incorrect decoding, e.g. for DNA storage. The target code words are grouped (102) into subsets and comprise identifying and remaining portions. The identifying portions of target code words corresponding to a same subset are identical. A first code symbol set of source code words is selected (103) for addressing the subsets. For the subsets,neighboring subsets are determined (104). The identifying portions of the target code words of neighboring subsets differ from those of the corresponding subset by up to a predetermined amount of symbols. Source code words are assigned (105) where the corresponding first code symbols address the same subset to said subset such that an amount of target code words of said subset having their remaining portions identical to their neighboring subsets corresponds to an optimization criterion.

Abstract translation: 生成代码簿，用于将源映射到目标代码字，其允许以不太好的解码的概率降低编码源数据，例如， 用于DNA存储。 目标码字被分组（102）成子集并且包括识别和剩余部分。 对应于同一子集的目标码字的识别部分是相同的。 选择用于寻址子集的源代码字的第一代码符号集合（103）。 对于子集，确定相邻子集（104）。 相邻子集的目标码字的识别部分与对应子集的识别部分不同，达到预定量的符号。 源代码字被分配（105），其中对应的第一代码符号将相同的子集寻址到所述子集，使得具有与其相邻子集相同的剩余部分的所述子集的目标代码字的量对应于优化准则。

公开(公告)号：WO2015130473A1

公开(公告)日：2015-09-03

申请号：PCT/US2015/015595

申请日：2015-02-12

Applicant: QUALCOMM INCORPORATED

Inventor： WANG, Xiao Feng ,  SHELLHAMMER, Stephen Jay

IPC: H04L25/49 ,  H04L25/03

CPC classification number: H03M5/16 ,  H03M5/145 ,  H03M7/46 ,  H04L25/03057 ,  H04L25/49 ,  H04L25/4923

Abstract: A method of line coding is disclosed that limits error propagation in a decision feedback equalizer (DFE) of a receiving device. A communications device receives a set of bits to be transmitted over a channel and divides the set of bits into a plurality of blocks based, at least in part, on a line coding scheme. The device then encodes each of the blocks of bits into a corresponding block of symbols based on the line coding scheme. Specifically, the line coding scheme has a non-uniform coding efficiency, wherein a first bit or a last bit of each block of bits is mapped to a single data symbol. For some embodiments, the line coding scheme may be a ternary line coding scheme that maps a block of 3k+1 bits to a corresponding block of 2k+1 symbols, where k is an integer greater than 1.

Abstract translation: 公开了一种限制接收设备的判决反馈均衡器（DFE）中的误差传播的线路编码方法。 通信设备接收要通过信道发送的一组比特，并且至少部分地基于线路编码方案将比特集合分成多个块。 然后，该设备基于线路编码方案将每个比特块块编码成相应的符号块。 具体地，线路编码方案具有不均匀的编码效率，其中每个比特块的第一比特或最后一比特被映射到单个数据符号。 对于一些实施例，线路编码方案可以是将3k + 1比特的块映射到2k + 1个符号的对应块的三元线编码方案，其中k是大于1的整数。

公开(公告)号：WO2011049014A1

公开(公告)日：2011-04-28

申请号：PCT/JP2010/068139

申请日：2010-10-15

Applicant: 日本電気株式会社 ,  岡村 利彦 ,  高橋 成五 ,  田島 章雄

Inventor： 岡村　利彦 ,  高橋　成五 ,  田島　章雄

IPC: H04L1/00 ,  H03M7/14 ,  H04L25/49

CPC classification number: H03M5/145 ,  H04L1/0057 ,  H04L25/49

Abstract: 　パリティ制御システムは、送信側で、送信する情報部分に対して変調符号化後に誤り訂正符号化を行ってパリティを生成し、受信側で、情報部分とパリティとを含む受信系列に対して誤り訂正符号復号及び変調符号復号を行う。送信側で、変調符号化を行った情報部分に対してヘッダを付加して誤り訂正符号化の入力となる情報ブロックを構成し、その情報ブロックを入力とする誤り訂正符号化によりパリティを生成し、ヘッダの値を用いてパリティのビットパタンを制御する。

Abstract translation: 一种奇偶校验控制系统，其中在发送端，要发送的信息部分被调制编码，然后纠错编码，从而产生奇偶校验，并且在接收端，包括信息部分和奇偶校验的接收序列是 纠错解码和调制解码。 在发送端，向调制编码的信息部分添加报头，形成输入到纠错编码处理的信息块。 然后将信息块输入到纠错编码处理，从而产生奇偶校验。 然后，头部的值用于控制奇偶校验的位模式。

公开(公告)号：WO2010094296A1

公开(公告)日：2010-08-26

申请号：PCT/EP2009/001112

申请日：2009-02-17

Applicant: THYSSENKRUPP PRESTA AG ,  HODOSSY, Sandor ,  TURMEZEI, Peter

Inventor： HODOSSY, Sandor ,  TURMEZEI, Peter

IPC: H04L25/49 ,  H03M5/12

CPC classification number: H04L25/4904 ,  H03M5/145

Abstract: The present invention relates to a method of decoding a digital signal which is encoded as a code sequence in Manchester code and which is submitted by a data source, comprising the following steps: a) determine the time (t) between two signal level changes from 0 to 1 or from 1 to 0, b) compare the time (t) of step a) with a preset time value (T) c) 1) if the time (t) differs from value (T) by more than a threshold (dt), then set an error flag, discard the present code sequence and request a new code sequence to be submitted from the data source, or 2) if the time (t) differs from value (T) by less than or equal to a threshold (dt), then the present code sequence will be accepted and decoded according to the Manchester code which is used for encoding and a new code sequence is requested from the data source and d) proceed with step a).

Abstract translation: 本发明涉及一种解码数字信号的方法，该数字信号被编码为曼彻斯特码中的码序列，并由数据源提交，包括以下步骤：a）确定两个信号电平变化之间的时间（t） 0至1或1至0，b）将步骤a）的时间（t）与预设时间值（T）进行比较c）1）如果时间（t）与值（T）不同，阈值 （dt），然后设置错误标志，丢弃当前代码序列并请求从数据源提交的新代码序列，或者2）如果时间（t）与值（T）不同，小于或等于 阈值（dt），则根据用于编码的曼彻斯特码接收和解码当前代码序列，并且从数据源请求新的代码序列，以及d）继续步骤a）。

公开(公告)号：WO2009060332A3

公开(公告)日：2009-09-11

申请号：PCT/IB2008054372

申请日：2008-10-23

Applicant: IBM ,  MITTELHOLZER THOMAS

Inventor： MITTELHOLZER THOMAS

IPC: H03M7/02

CPC classification number: H03M5/145 ,  H03M7/02 ,  H03M7/3088

Abstract: Methods and apparatus are provided for modulation coding a stream of binary input data. A 4-ary enumerative encoding algorithm is applied to the input bit-stream to produce a succession of 4-ary output symbols. The 4-ary algorithm is operative to simultaneously encode respective generalized Fibonacci codes in the odd and even interleaves of the input bit-stream. The bits of each successive 4-ary output symbol are then interleaved, producing an output bit-stream which has global and interleaved run-length constraints. Inverting the bits of the 4-ary output symbols produces an output bit-stream with (G, I) -constraints as in the PRML (G, I) codes used in reverse-concatenation modulation systems. Corresponding decoding systems are also provided.

Abstract translation: 提供了用于对二进制输入数据流进行调制编码的方法和装置。 4进制枚举编码算法被应用于输入比特流以产生一系列4进制输出符号。 4进制算法可用于在输入比特流的奇数和偶数交织中同时编码相应的广义斐波纳契码。 然后每个连续的4进制输出符号的比特被交织，产生具有全局和交织的游程长度约束的输出比特流。 反转四元输出符号的位产生与（G，I）约束的输出比特流，如反向级联调制系统中使用的PRML（G，I）码一样。 还提供了相应的解码系统。