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公开(公告)号：WO2003088489A2
公开(公告)日：2003-10-23
申请号：PCT/US2003/011047
申请日：2003-04-11
Applicant: FAIRCHILD SEMICONDUCTOR CORPORATION
Inventor： MCDONALD, James J., II. , HULFACHOR, Ronald, B. , WUNDERLICH, Jim
IPC: H03L
CPC classification number: H03L7/0891 , H03L7/095 , H03L7/0995 , H03L7/10 , H03L2207/14 , H04L7/033 , H04L7/044 , H04L7/10
Abstract: A phase locked loop circuit is used to provide timing clocks for bit recovery from a serial data flow. The system locked to a SYNC signal, preferably a lower frequency fifty percent duty cycle square wave with a period equal to the time of a fully framed serial data word. When a start signal transition is detected the system is prevented from trying to lock onto the data signal edge transitions. But, the system provides a signal suitable for clockingin the individual data bits.
Abstract translation: 锁相环电路用于提供从串行数据流中进行位恢复的定时时钟。 该系统锁定为SYNC信号，优选地是具有等于完全成帧的串行数据字的时间的周期的较低频率百分之五十的占空比方波。 当检测到启动信号转换时，系统被阻止试图锁定到数据信号边沿转换。 但是，该系统提供适合于在各个数据位上定时的信号。
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公开(公告)号：WO2003017494A1
公开(公告)日：2003-02-27
申请号：PCT/DE2002/002885
申请日：2002-08-06
Applicant: SIEMENS AKTIENGESELLSCHAFT , STEINBAUER, Christian
Inventor： STEINBAUER, Christian
IPC: H03L7/099
CPC classification number: H04L7/033 , H03J1/0008 , H03J7/065 , H03L7/18 , H04L7/10
Abstract: Die vorliegende Erfindung betrifft ein Verfahren und eine Vorrichtung zur Frequenzsynchronisation einer Mobilstation mit einer Basisstation. Die Frequenzsynchronisation wird auch bei einer starken Verstimmung des Oszillatorkristalls ermöglicht, indem der Suchbereich entsprechend gewählt wird.
Abstract translation: 本发明涉及一种方法，以及用于与基站的移动台的频率同步的装置。 频率同步是可能的，即使在由搜索范围中的振荡器晶体的强失谐相应地选择。
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公开(公告)号：WO2003009534A1
公开(公告)日：2003-01-30
申请号：PCT/JP2002/007197
申请日：2002-07-16
IPC: H04L12/28
CPC classification number: H04W4/008 , H04J3/0658 , H04L7/10 , H04L45/02 , H04L63/0869 , H04L63/18 , H04M1/7253 , H04M2250/02 , H04M2250/14 , H04W4/80 , H04W8/005 , H04W12/06 , H04W40/246 , H04W56/00 , H04W84/18
Abstract: A communication system and method capable of easily and rapidly starting a communication. A cellular telephone (52) has a non−contact IC card for communicating with a reader/writer of a personal computer (51) by an electromagnetic wave. When the cellular telephone (52) is placed in the proximity of the personal computer (51) and an electromagnetic wave radiated from the reader/writer is received by the non−contact IC card, the cellular telephone (52) reports the card ID set in the non−contact IC card to the personal computer (51). The personal computer (51) establishes synchronization in pico−net between the cellular telephone (52) and a PDA (53). When a Bluetooth device name of the cellular telephone (52) and the PDA (53) is fetched, the cellular telephone (52) is identified as a communication mate according to the Bluetooth device name which has been reported as the card ID in advance. The present invention can be applied to an information processing apparatus such as a personal computer and a cellular telephone.
Abstract translation: 能够容易且快速地开始通信的通信系统和方法。 蜂窝电话（52）具有用于通过电磁波与个人计算机（51）的读取器/写入器通信的非接触式IC卡。 当蜂窝电话（52）被放置在个人计算机（51）附近并且由非接触式IC卡接收到从读取器/写入器辐射的电磁波时，蜂窝电话（52）报告卡ID集 在非接触IC卡到个人计算机（51）。 个人计算机（51）在蜂窝电话（52）和PDA（53）之间的微微网中建立同步。 当取出蜂窝电话（52）和PDA（53）的蓝牙设备名称时，根据已经作为卡ID预先报告的蓝牙设备名称将蜂窝电话（52）识别为通信伙伴。 本发明可以应用于个人计算机和蜂窝电话等信息处理装置。
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公开(公告)号：WO02052776A1
公开(公告)日：2002-07-04
申请号：PCT/US2001/044692
申请日：2001-11-29
CPC classification number: H04L7/033 , H03L7/107 , H03L7/181 , H04J3/0685 , H04L7/10
Abstract: A method and system provide a stable reference clock for use in a communication system. A phase-locked loop (PLL) receives an input clock signal with potentially unacceptable levels of jitter and wander. The PLL provides a synchronized output clock with significantly reduced jitter and wander. The PLL nominally uses a digital-to-analog converter (DAC) to control a voltage-controlled oscillator (VCO). Applying a loop filter function to the phase difference between the input clock and the output clock generates control values for the DAC. Loop filter adaptation is based on control value averages, which enhances stability and frequency locking performance. Frequency lock detection is based on the consistency of the DAC control values, rather than on a predetermined target value, making the PLL a self-calibrating system. The long-term average of the control value in the locked state may be stored for later use as an initial DAC setting.
Abstract translation: 方法和系统提供用于通信系统的稳定的参考时钟。 锁相环（PLL）接收具有潜在不可接受的抖动和漂移水平的输入时钟信号。 PLL提供了一个同步的输出时钟，显着减少抖动和漂移。 PLL通常使用数模转换器（DAC）来控制压控振荡器（VCO）。 对输入时钟和输出时钟之间的相位差应用环路滤波器功能可以产生DAC的控制值。 环路滤波器适应是基于控制值平均值，这增强了稳定性和频率锁定性能。 频率锁定检测基于DAC控制值的一致性，而不是基于预定的目标值，使PLL成为自校准系统。 锁定状态下的控制值的长期平均值可以作为初始DAC设置存储起来供以后使用。
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公开(公告)号：WO02030078A1
公开(公告)日：2002-04-11
申请号：PCT/JP2001/008789
申请日：2001-10-05
CPC classification number: H04L25/085 , H04J3/0638 , H04L7/046 , H04L7/10 , H04L25/062 , H04L25/066 , H04L25/4919
Abstract: A first initialization pattern signal having alternate maximum and minimum signal levels and a second initializing pattern signal having a predetermined arrangement of all the signal levels are used. In a ring network including data transmitters (100), a transmitting section (110) of each data transmitter sends the first initialization pattern signal to the next-stage data transmitter when the power is turned on or the transmitter is reset. A receiving section (120) establishes clock synchronization according to the received first initialization pattern signal. When the synchronization of all the data transmitters is established, the transmitting section (110) sends the second initialization pattern signal to the next-stage data transmitter, and the receiving section (120) sets judgment levels for the signal levels according to the received initialization pattern signal. When the judging levels are set by all the data transmitters, data is started to be transmitted and received.
Abstract translation: 使用具有交替的最大和最小信号电平的第一初始化模式信号和具有所有信号电平的预定布置的第二初始化模式信号。 在包括数据发送器（100）的环形网络中，当电源接通或发送器被复位时，每个数据发送器的发送部分（110）将第一初始化模式信号发送到下一级数据发送器。 接收部分（120）根据接收到的第一初始化模式信号建立时钟同步。 当建立所有数据发射机的同步时，发送部分（110）将第二初始化模式信号发送给下一级数据发射机，并且接收部分（120）根据接收的初始化设置信号电平的判定电平 模式信号。 当所有数据发射机设置判断级别时，开始发送和接收数据。
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Patent Agency Ranking
公开(公告)号：WO02030077A1
公开(公告)日：2002-04-11
申请号：PCT/JP2001/008786
申请日：2001-10-05
CPC classification number: H04L25/085 , H04J3/0638 , H04L7/046 , H04L7/10 , H04L25/062 , H04L25/066 , H04L25/4919
Abstract: A judgment level setting method for judging accurately the signal level in a multi-level transmission for transmitting data by allocating data of one or more bits to the signal level as a data symbol and a data receiver are disclosed. A data transmitter sends an initialization pattern signal when the power is turned on or the transmitter is reset. The data receiver establishes the clock synchronization according to the received initialization pattern signal, sets a judgement level for threshold judgment of signal level, and starts receiving data.
Abstract translation: 一种判断电平设定方法，用于通过将信号电平中的一个或多个位的数据分配为数据符号和数据接收器来准确地判断用于发送数据的多电平传输中的信号电平。 当电源打开或发送器复位时，数据发送器发送初始化模式信号。 数据接收机根据接收到的初始化模式信号建立时钟同步，设置信号电平阈值判断的判断电平，并开始接收数据。
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公开(公告)号：WO0008800A9
公开(公告)日：2000-11-16
申请号：PCT/US9916276
申请日：1999-07-26
Applicant: JUNIPER NETWORKS
Inventor： LIENCRES BJORN O
CPC classification number: H04L49/9021 , H04J3/0632 , H04L7/041 , H04L7/10 , H04L12/56 , H04L12/5601 , H04L29/06 , H04L45/00 , H04L47/6225 , H04L49/108 , H04L49/203 , H04L49/3081 , H04L49/608 , H04L49/90 , H04L49/901 , H04L49/9047 , H04L69/22 , H04L2012/5652 , H04L2012/5674 , H04L2012/5679 , H04Q11/0478
Abstract: A method and apparatus for synchronizing components operating isochronously that are coupled by independent links. The apparatus includes a synchronization circuit having a first and second buffer, each including an input port coupled to an external link, an output port, a read pointer and a write pointer. The read pointer indicates a next location in a respective buffer to be read in transferring data out on the output port. The write pointer indicates a next location in the respective buffer to be written when receiving data on the input port and is configured to automatically increment upon receipt of a first data bit on a respective external link. A trigger circuit is coupled to each link for receiving external trigger signals. Each external trigger signal is included along with data transmitted on the link and indicates when data is present on a respective link. A counter is coupled to the trigger circuit. The counter includes a trigger input and a predefined delay period. After receipt of a first of the external trigger signals on the trigger input, the counter is operable to output a read enable signal to each of the read pointers after the delay period has expired.
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公开(公告)号：WO00008800A3
公开(公告)日：2000-05-11
申请号：PCT/US1999/016276
申请日：1999-07-26
CPC classification number: H04L49/9021 , H04J3/0632 , H04L7/041 , H04L7/10 , H04L12/56 , H04L12/5601 , H04L29/06 , H04L45/00 , H04L47/6225 , H04L49/108 , H04L49/203 , H04L49/3081 , H04L49/608 , H04L49/90 , H04L49/901 , H04L49/9047 , H04L69/22 , H04L2012/5652 , H04L2012/5674 , H04L2012/5679 , H04Q11/0478
Abstract: A method and apparatus for synchronizing components operating isochronously that are coupled by independent links. The apparatus includes a synchronization circuit having a first and second buffer, each including an input port coupled to an external link, an output port, a read pointer and a write pointer. The read pointer indicates a next location in a respective buffer to be read in transferring data out on the output port. The write pointer indicates a next location in the respective buffer to be written when receiving data on the input port and is configured to automatically increment upon receipt of a first data bit on a respective external link. A trigger circuit is coupled to each link for receiving external trigger signals. Each external trigger signal is included along with data transmitted on the link and indicates when data is present on a respective link. A counter is coupled to the trigger circuit. The counter includes a trigger input and a predefined delay period. After receipt of a first of the external trigger signals on the trigger input, the counter is operable to output a read enable signal to each of the read pointers after the delay period has expired.
Abstract translation: 一种用于使通过独立链路耦合的等时运行的组件同步的方法和装置。 该装置包括具有第一和第二缓冲器的同步电路，每个缓冲器包括耦合到外部链路的输入端口，输出端口，读取指针和写入指针。 读指针指示在输出端口上传送数据时要读取的相应缓冲器中的下一个位置。 写指针指示在接收输入端口上的数据时要写入的相应缓冲器中的下一位置，并且被配置为在接收到相应外部链路上的第一数据位时自动递增。 触发电路耦合到每个链路以用于接收外部触发信号。 每个外部触发信号与在链路上发送的数据一起被包括，并且指示何时在相应的链路上存在数据。 计数器耦合到触发电路。 计数器包括触发输入和预定义的延迟时间。 在触发输入上接收到第一外部触发信号之后，计数器可操作以在延迟时间期满之后将读使能信号输出到每个读指针。
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99.发明申请METHOD AND APPARATUS FOR BIT SYNCHRONIZATION IN OPTICAL COMMUNICATION AND NETWORKING SYSTEMS 审中-公开在光通信和网络系统中用于位同步的方法和设备
公开(公告)号：WO0002334A3
公开(公告)日：2000-04-27
申请号：PCT/US9911894
申请日：1999-05-28
Applicant: SUN MICROSYSTEMS INC
Inventor： DAVIDSON HOWARD L
CPC classification number: H04L7/0075 , H04J14/08 , H04L7/0037 , H04L7/10
Abstract: An apparatus and method are provided for bit synchronization in an optical time division multiplexed communication system. The apparatus is couplable to an optical gate, such as an optical demultiplexer. The apparatus includes a programmable optical delay line couplable to an input clock; an optical synchronizer coupled to the programmable optical delay line and couplable to the optical gate; and a processor coupled to the programmable optical delay line and to the optical synchronizer. The processor includes program instructions to track bit synchronization between a clock pulse and a selected data bit during a communication session; and when a bit tracking range is approaching a predetermined limit, the processor has further instructions to interrupt the communication session, return the bit tracking range to a zero offset and correspondingly adjust a programmable delay, and resume the communication session.
Abstract translation: 提供了一种用于光时分复用通信系统中的比特同步的设备和方法。 该设备可耦合到光学门，例如光学解复用器。 该设备包括可耦合到输入时钟的可编程光学延迟线; 光学同步器，其耦合到所述可编程光学延迟线并且可耦合到所述光学门; 以及耦合到可编程光学延迟线和光学同步器的处理器。 处理器包括用于在通信会话期间跟踪时钟脉冲和所选数据比特之间的比特同步的程序指令; 并且当比特跟踪范围接近预定极限时，处理器还具有中断通信会话的指令，将比特跟踪范围返回到零偏移并相应地调整可编程延迟，并且恢复通信会话。
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公开(公告)号：WO9946886A3
公开(公告)日：2000-03-02
申请号：PCT/US9904437
申请日：1999-02-26
Applicant: EPIGRAM INC
Inventor： OJARD ERIC , TRACHEWSKY JASON , HOLLOWAY JOHN T , FRANK EDWARD H , PETERSON KEVIN H
IPC: H04L13/08 , H04L1/00 , H04L7/027 , H04L7/04 , H04L7/10 , H04L12/413 , H04L25/03 , H04L27/26 , H04L29/06 , H04L29/10 , G06F13/12 , H04L25/497 , H04L27/38
CPC classification number: H04L12/40032 , H04L1/0054 , H04L1/0065 , H04L7/027 , H04L7/041 , H04L7/10 , H04L12/40013 , H04L12/413 , H04L25/03057 , H04L27/2647
Abstract: A network interface is presented that receives packet data from a shared medium and accomplishes the signal processing required to convert the data packet to host computer formatted data separately from receiving the data packet. The network interface receives the data packet, converts the analog signal to a digitized signal, and stores the resulting sample packet in a storage queue. An off-line processor, which may be the host computer itself, performs the signal processing required to interpret the sample packet. In transmission, the off-line process converts host-formatted data to a digitized version of a transmission data packet and stores that in a transmission queue. A transmitter converts the transmission data packet format and transmits the data to the shared medium.
Abstract translation: 提出了一种从共享介质接收分组数据并实现将数据分组转换为主计算机格式化数据所需的信号处理的网络接口，与接收数据分组不同。 网络接口接收数据包，将模拟信号转换为数字信号，并将生成的样本包存储在存储队列中。 可能是主计算机本身的离线处理器执行解释样本分组所需的信号处理。 在传输中，离线过程将主机格式的数据转换为传输数据分组的数字化版本，并将其存储在传输队列中。 发射机转换传输数据包格式并将数据发送到共享介质。
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