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公开(公告)号：WO1989002677A1
公开(公告)日：1989-03-23
申请号：PCT/JP1988000923
申请日：1988-09-13
申请人： FUJITSU LIMITED , ISHII, Yasuhiro , FUKUSHI, Isao
发明人： FUJITSU LIMITED
IPC分类号： H03K19/00
CPC分类号： H03K3/356017 , H03K19/0016
摘要： An emitter follower circuit has series circuits, each consisting of an emitter follower transistor (Q3, Q4), a current source, and a current source resistor connected to the emitter side of the emitter follower transistor (Q3, Q4). The source resistors are MOS transistors (N4, N5), which are switched on and off by control signals so that they have conduction and cutoff states. Between the source and the drain of each MOS transistors (N4, N5), current path means (R1, R2) is provided which has a resistance greater than the on-resistance of the MOS transistors to permit a very small current to flow, at least when said MOS transistors are rendered nonconductive.
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公开(公告)号：WO2023075252A1
公开(公告)日：2023-05-04
申请号：PCT/KR2022/015744
申请日：2022-10-17
申请人： 삼성전자 주식회사
摘要： 마이크, 통신 회로, 메모리, 및 상기 마이크, 상기 통신 회로, 및 상기 메모리와 작동적으로 연결된 프로세서를 포함하는 전자 장치가 개시된다. 상기 메모리는, 상기 프로세서에 의해 실행 시에, 상기 전자 장치가, 상기 통신 회로를 통해 제1 외부 전자 장치로부터 오디오 데이터 요청을 수신하고, 지정된 조건에 기반하여, 상기 통신 회로를 통해 연결된 제2 외부 전자 장치와 동일한 시간 구간에 상기 마이크를 통해 획득된 오디오 데이터를 이용하여 제1 오디오 패킷을 생성하고, 상기 제2 외부 전자 장치가 생성한 제2 오디오 패킷과의 생성 순서를 비교하기 위한 정보를 상기 제1 오디오 패킷에 삽입하고, 상기 제1 오디오 패킷을 상기 통신 회로를 통해 상기 제1 외부 전자 장치로 전송하도록 하는 하나 이상의 인스트럭션들(instructions)을 저장할 수 있다. 이 외에도 명세서를 통해 파악되는 다양한 실시 예가 가능하다.
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公开(公告)号：WO2023000485A1
公开(公告)日：2023-01-26
申请号：PCT/CN2021/120145
申请日：2021-09-24
申请人： 长鑫存储技术有限公司
发明人： 谷银川
IPC分类号： H03K19/094 , H03K19/00
摘要： 一种锁存电路及方法、电子设备，涉及集成电路技术领域。该锁存电路（100）包括：传输模块（110）、锁存模块（120）和控制模块（130）；其中，传输模块，用于将输入信号传输至锁存模块；锁存模块，用于在置位信号或复位信号为低电平时，锁存输入信号或输出输入信号；控制模块，用于在置位信号或复位信号为高电平时，控制传输模块和锁存模块之间无法形成电流泄漏通路。
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124.发明申请
公开(公告)号：WO2022159918A1
公开(公告)日：2022-07-28
申请号：PCT/US2022/070089
申请日：2022-01-07
发明人： JIANG, Jize , DELIGOZ, Ilker
IPC分类号： H03K19/00
摘要： Certain aspects of the present disclosure provide a circuit for clock signal generation. The circuit generally includes a plurality of clock generation circuits configured to generate a plurality of clock signals from a clock signal, and a power supply circuit having an output coupled to power supply inputs of the plurality of clock generation circuits. The circuit may also include a capacitor array coupled to the output of the power supply circuit and include a plurality of capacitive elements, the capacitor array being configured to selectively couple each of the plurality of capacitive elements to the output of the power supply circuit based on a quantity of one or more active clock generation circuits of the plurality of clock generation circuits.
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公开(公告)号：WO2022041154A1
公开(公告)日：2022-03-03
申请号：PCT/CN2020/112289
申请日：2020-08-28
申请人： 华为技术有限公司
IPC分类号： G01R31/317 , H03K19/00
摘要： 本申请实施例公开了一种保持时间裕量的检测电路，涉及电路技术领域，改善了现有技术中芯片内保持时间裕量的检测精度较差的问题。具体方案为：检测电路包括：发生器和判决电路；发生器包括至少一组测试电路，每组测试电路包括N个第一寄存器、N个第二寄存器，以及N个数据延迟单元，N个数据延迟单元的时延依次递增，相邻两个数据延迟单元之间的时延差小于或等于预设值；其中，N个第一寄存器的数据输出端分别与N个数据延迟单元的输入端连接，N个数据延迟单元的输出端分别与N个第二寄存器的数据输入端连接，N个第二寄存器的数据输出端与所述判决电路连接。
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公开(公告)号：WO2022036448A1
公开(公告)日：2022-02-24
申请号：PCT/CA2021/051142
申请日：2021-08-18
发明人： MALLINSON, A. Martin
IPC分类号： H03K19/00
摘要： Combinatorial logic circuits with feedback, which include at least two combinatorial logic elements, are disclosed. At least one of the combinatorial logic elements receives an external input (i.e., from outside the circuit), at least one of the combinatorial logic elements receives an input that is feedback of the circuit output, and at least one of the combinatorial logic elements receives an input that is neither an external input nor an output of the circuit but rather is from another of the combinatorial logic elements and thus only "implicit" to the circuit. No staticizers are needed; the logic circuits effectively create implicit equations to perform functions that were previously thought to require sequential logic. The combinatorial logic circuits result in a stable output (in some instances after a brief period of time) due to the implicit equations, rather than achieving stability from an explicit expression of some input to the circuit.
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127.发明申请
公开(公告)号：WO2021154881A1
公开(公告)日：2021-08-05
申请号：PCT/US2021/015326
申请日：2021-01-27
发明人： YADAV, Kshitij
摘要： Certain aspects of the present disclosure provide circuitry connecting an output of voltage reference circuitry powered by a relatively high voltage to an input of a voltage buffer configured to generate a voltage lower than the high voltage. The connecting circuitry prevents the high voltage from reaching the input of the voltage buffer. One example electronic circuit generally includes a voltage reference circuit configured to be powered by a relatively higher voltage, a buffer circuit configured to generate a relatively lower voltage as compared to the relatively higher voltage, and circuitry coupled between an output of the voltage reference circuit and an input of the buffer circuit, the circuity being configured to prevent the higher voltage from reaching the input of the buffer circuit.
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公开(公告)号：WO2021145987A1
公开(公告)日：2021-07-22
申请号：PCT/US2020/064458
申请日：2020-12-11
发明人： SHETTY, Rohit , TAN, Chiew-Guan , LYNCH, Gregory
IPC分类号： H03K3/012 , H03K3/356 , H03K19/0185 , H03K19/003 , H03K19/00 , H03K19/0013 , H03K19/0016 , H03K19/00315 , H03K19/018528 , H03K3/35613 , H03K3/356182
摘要： Certain aspects of the present disclosure generally relate to a level- shifting circuit (100). The level-shifting circuit generally includes a first pull-up path (102, 170) having at least one first diode (170) and at least one first transistor (102), and a second pull-up path (108, 174) having at least one second diode (174) and at least one second transistor (108). The level-shifting circuit may also include a first pull-down path (124, 120) having a third transistor (120) and a fourth transistor (124), wherein the fourth transistor (124) is coupled between the third transistor (120) and the first diode (170); a second pull-down path (126, 130) having a fifth transistor (126) and a sixth transistor (130), wherein the sixth transistor (130) is coupled between the fifth transistor (126) and the second diode (174); and an overvoltage protection circuit (125, 131) coupled to gates of the fourth transistor (124) and the sixth transistor (130).
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129.发明申请
公开(公告)号：WO2021108797A1
公开(公告)日：2021-06-03
申请号：PCT/US2020/070122
申请日：2020-06-04
发明人： LASSEN, Jacob Lunn
IPC分类号： G06F11/07 , G06F1/24 , H03K19/00 , H03K19/0175
摘要： An electrical system includes an integrated circuit device including input/output (I/O) pins, a reset circuit, and an I/O circuit. The I/O circuit is operably coupled to the I/O pins. The I/O circuit is configured to selectively operate the I/O pins in an electrically floating state responsive to a system reset signal transmitted by the reset circuit. The I/O circuit is further configured to selectively operate the I/O pins in the electrically floating state responsive to a signal provided by a timer circuit independently from the reset circuit.
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130.发明申请
公开(公告)号：WO2021080671A1
公开(公告)日：2021-04-29
申请号：PCT/US2020/046704
申请日：2020-08-17
申请人： INTEL CORPORATION
发明人： ZLOTNIK, Leon , ZLOTNIK, Lev , ANDERSON, Jeremy
摘要： An asynchronous multi-cycle reset synchronization circuit that can correlate any number of resets and synchronous clocks with simultaneous reset de-assertion and removal of reset assertion crossing hazards. The asynchronous multi-cycle reset synchronization circuit can also be paired with a synchronous multi-cycle reset synchronization circuit to correlate same domain asynchronous and synchronous resets. Also described is a synchronous reset multi-cycle synchronization circuit that correlates with any number of asynchronous resets and guarantees simultaneous reset de-assertion.
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