公开(公告)号：WO2022081321A1

公开(公告)日：2022-04-21

申请号：PCT/US2021/051697

申请日：2021-09-23

Applicant: QUALCOMM INCORPORATED

Inventor： PRESSWALA, Aliasgar ,  CHEN, Wilson Jianbo ,  TAN, Chiew-Guan ,  JALILIZEINALI, Reza

IPC: H03K3/356

Abstract: An output driver in an integrated circuit includes a voltage shifter. The output driver has a low voltage section configured to provide a low voltage signal responsive to an input signal and a high voltage section configured to provide a high voltage signal responsive to the input signal. A first biasing circuit is configured to provide a bias to a first transistor in the high voltage section such that the bias is modified during a transition in the output signal. A second biasing circuit is configured to turn on a second transistor in the high voltage section when the output signal is at a low voltage level. The second transistor is configured to discharge a terminal of the first transistor. The input signal switches between 0 Volts and 0.9 Volts. The output signal switches between 0 Volts and 1.2 Volts or between 0 Volts and 1.8 Volts.

公开(公告)号：WO2015160452A2

公开(公告)日：2015-10-22

申请号：PCT/US2015/019958

申请日：2015-03-11

Applicant: QUALCOMM INCORPORATED

Inventor： CHEN, Wilson Jianbo ,  TAN, Chiew-Guan ,  JALILIZEINALI, Reza

IPC: H03K5/24

CPC classification number: H03K5/08 ,  H03K5/24 ,  H03K19/00315

Abstract: An input receiver for stepping down a high-voltage domain input signal into a low-voltage-domain stepped-down signal includes a waveform chopper. The waveform chopper chops the high-voltage domain input signal into a first chopped signal and a second chopped signal. A high-voltage-domain receiver combines the first chopped signal and the second chopped signal into a high-voltage-domain combined signal. A step-down device converts the high-voltage-domain combined signal into a stepped-down low-voltage-domain signal.

Abstract translation: 用于将高电压域输入信号降压为低电压域降阶信号的输入接收器包括波形斩波器。 波形斩波器将高电压域输入信号切成第一斩波信号和第二斩波信号。 高电压域接收器将第一斩波信号和第二斩波信号组合成高电压域组合信号。 降压装置将高电压域组合信号转换成降压低电压域信号。

公开(公告)号：WO2019177709A1

公开(公告)日：2019-09-19

申请号：PCT/US2019/016037

申请日：2019-01-31

Applicant: QUALCOMM INCORPORATED

Inventor： MISHRA, Lalan Jee ,  WIETFELDT, Richard Dominic ,  O'SHEA, Helena Deirdre ,  ROETHIG, Wolfgang ,  CHUN, Christopher Kong Yee ,  CHEN, ZhenQi ,  DAVENPORT, Scott ,  TAN, Chiew-Guan ,  CHEN, Wilson ,  SRIKANTIAH, Umesh

IPC: H04B1/12 ,  G06F13/42

Abstract: Systems, methods, and apparatus for data communication are provided. A method performed by a bus master includes terminating transmission of a first datagram by signaling a first bus park cycle on a serial bus, causing a driver to enter a high- impedance state, opening an interrupt window by providing a first edge in a clock signal transmitted on a second line of the serial bus, closing the interrupt window by providing a second edge in the clock signal, signaling a second bus park cycle on the serial bus, initiating an arbitration process when an interrupt was received on the first line of the serial bus while the interrupt window was open, and initiating a transmission of a second datagram when an interrupt was not received on the first line of the serial bus while the interrupt window was open.

公开(公告)号：WO2017099937A1

公开(公告)日：2017-06-15

申请号：PCT/US2016/061392

申请日：2016-11-10

Applicant: QUALCOMM INCORPORATED

Inventor： MISHRA, Lalan ,  CHUN, Chrisotpher Kong Yee ,  TAN, Chiew-Guan ,  LEE, Gordon ,  SUTTON, Todd

IPC: G06F13/42

CPC classification number: H04L47/12 ,  G06F13/4278 ,  G06F13/4295 ,  H04L5/14 ,  H04L49/109 ,  H04W28/0221 ,  H04W52/0229 ,  Y02D70/122 ,  Y02D70/26

Abstract: System, methods, and apparatus are described that facilitate signaling between devices over a single bi-directional line. In an example, the apparatus couples a first device to a second device via a single bi-directional line, indicates initiation of a first action, initiated at the first device, by sending a first single transition on the single bi-directional line from the first device to the second device, and indicates initiation of a second action, initiated at the second device, by sending a second single transition on the single bi-directional line from the second device to the first device. In another example, a first device initiates a first action, indicates initiation of the first action by generating a first event on a single bi-directional line, and receives an indication of a second action initiated at a second device by observing a second event on the single bi-directional line.

Abstract translation: 描述了便于在单个双向线路上的设备之间的信令的系统，方法和设备。 在一个示例中，该设备经由单个双向线路将第一设备耦合到第二设备，通过在单个双向线路上从第一设备发起的第一单动态转换指示在第一设备处发起的第一动作的发起 并且指示在所述第二设备处发起的通过在所述单个双向线上从所述第二设备向所述第一设备发送第二单个转换的第二动作的发起。 在另一示例中，第一设备发起第一动作，通过在单个双向线上生成第一事件来指示第一动作的发起，并且通过观察第二事件在第二设备处发起的第二动作的指示 单一的双向线。

公开(公告)号：WO2016137639A1

公开(公告)日：2016-09-01

申请号：PCT/US2016/014990

申请日：2016-01-26

Applicant: QUALCOMM INCORPORATED

Inventor： CHEN, Wilson Jianbo ,  TAN, Chiew-Guan ,  JALILIZEINALI, Reza

IPC: H03K19/003

CPC classification number: H03K17/26 ,  H03K17/18 ,  H03K19/00315 ,  H03K19/00361

Abstract: A back-power prevention circuit (205) is provided that protects a buffer transistor (MPl) from back-power during a back-power condition by charging a signal lead (PCLT) coupled to a gate of the buffer transistor (MPl), to a pad voltage (PadSig) and by charging a body (235) of the buffer transistor (MPl) to the pad voltage (PadSig, NW).

Abstract translation: 提供了一种背功率防止电路（205），其通过对耦合到缓冲晶体管（MP1）的栅极的信号引线（PCLT）进行充电来在后功率状态期间保护缓冲晶体管（MP1）免于后功率， 垫片电压（PadSig），并通过将缓冲晶体管（MP1）的主体（235）充电到焊盘电压（PadSig，NW）。

公开(公告)号：WO2023086243A2

公开(公告)日：2023-05-19

申请号：PCT/US2022/048591

申请日：2022-11-01

Applicant: QUALCOMM INCORPORATED

Inventor： CHEN, Wilson Jianbo ,  TAN, Chiew-Guan

IPC: H03K19/003 ,  H03K19/0185

Abstract: An aspect of the disclosure relates to an apparatus including an output driver, including: a first p-channel metal oxide semiconductor field effect transistor (PMOS FET); a second PMOS FET coupled in series with the first PMOS FET between an upper voltage rail and an output; a first n-channel metal oxide semiconductor field effect transistor (NMOS FET); and a second NMOS FET coupled in series with the first NMOS FET between the output and a lower voltage rail; a first predriver coupled to gates of the first and second PMOS FETs and first and second NMOS FETs; and a second predriver coupled to the gates of the first and second PMOS FETs and first and second NMOS FETs.

公开(公告)号：WO2020046506A1

公开(公告)日：2020-03-05

申请号：PCT/US2019/043564

申请日：2019-07-26

Applicant: QUALCOMM INCORPORATED

Inventor： CHEN, Wilson Jianbo ,  TAN, Chiew-Guan ,  RAO, Sumit

IPC: H03K19/003 ,  H03K19/0185

Abstract: Aspects generally relate to receivers, and in particular to a receiver that converts a high-voltage input signal (102) into a low-voltage signal (135). The high voltage input signal (102) is split into a upper portion (125) and a lower portion (130). The upper portion is coupled to a high input receiver (115) that is powered by dynamic supply shifters that can vary supply voltage during operation to optimize switching.

公开(公告)号：WO2013109693A1

公开(公告)日：2013-07-25

申请号：PCT/US2013/021843

申请日：2013-01-17

Applicant: QUALCOMM INCORPORATED

Inventor： CHEN, Wilson J. ,  TAN, Chiew-Guan

IPC: H03K19/0175

CPC classification number: H03K19/017545

Abstract: Output driver feedback circuitry is configured to sense an amount of output capacitance of an output pad and to adjust the strength of the output driver accordingly. The feedback circuitry adjusts the output driver within a single cycle. A chain of delay reference signals is generated by representative capacitive loads that replicate a range of actual output loads. Adjustments to the output driver are based on a comparison of the delay reference signals with output of the output driver.

Abstract translation: 输出驱动器反馈电路被配置为感测输出焊盘的输出电容量并相应地调整输出驱动器的强度。 反馈电路在一个周期内调整输出驱动器。 延迟参考信号链是通过复制实际输出负载范围的典型容性负载来产生的。 输出驱动器的调整基于延迟参考信号与输出驱动器输出的比较。

公开(公告)号：WO2013109688A1

公开(公告)日：2013-07-25

申请号：PCT/US2013/021836

申请日：2013-01-17

Applicant: QUALCOMM INCORPORATED

Inventor： CHEN, Wilson J. ,  TAN, Chiew-Guan

IPC: H03K5/13

CPC classification number: H03K5/13

Abstract: Process, voltage and temperature corners of an on-chip device under calibration are obtained by comparing the outputs of different on-chip components such as active onchip components and passive-on chip components in response to an input. A first onchip delay line including a number of active devices, which generate an array of outputs (D[ ]) at different stages of the delay. A second on-chip delay line generates a single output (CLK). A DFF array samples the array of outputs (D[ ]) with the single output clock CLK. The different delay variations in different process and temperature corners cause different outputs from the DFF array. The different outputs from the DFF array provide information about the process and temperature corner that can be for rapid calibration of the on-chip device under calibration within one cycle of the CLK.

Abstract translation: 通过比较不同片上组件的输出，例如有源芯片组件和无源芯片组件对输入进行比较，可获得片上器件的校准过程，电压和温度转角。 包括多个有源器件的第一片上延迟线，其在延迟的不同阶段产生输出阵列（D []）。 第二个片内延迟线产生单个输出（CLK）。 DFF阵列用单个输出时钟CLK采样输出阵列（D []）。 不同工艺和温度角的不同延迟变化会导致DFF阵列的不同输出。 来自DFF阵列的不同输出提供了有关可在CLK周期内校准下片内器件快速校准的过程和温度角的信息。

公开(公告)号：WO2023080991A1

公开(公告)日：2023-05-11

申请号：PCT/US2022/046103

申请日：2022-10-07

Applicant: QUALCOMM INCORPORATED

Inventor： CHEN, Wilson Jianbo ,  PRESSWALA, Aliasgar ,  TAN, Chiew-Guan

IPC: H03K19/0185 ,  H03K19/003

Abstract: An aspect of the disclosure relates to an apparatus (300) including a first field effect transistor (FET) (Ml) including a first gate configured to receive a first input signal (Vlhv) that varies in accordance with a first voltage domain (0.9V to 1.8V); and a first inverter (310) including a first input configured to receive a second input signal (V2lv/) that varies in accordance with a second voltage domain (0 to 0.9v), and a first output configured to generate a first output signal (Vllv) that varies in accordance with the second voltage domain (0 to 0.9V), wherein the first output signal is based on the first and second input signals, and wherein the first FET (Ml) and the first inverter (310: M2, M3) are coupled in series between first and second voltage rails (VDDIX, VSSX). Per another aspect (fig. 7), the apparatus includes additional circuitry (710) to allow the apparatus to process signals in accordance with a third voltage domain (0.5V to 1.1V).