公开(公告)号：WO2019190688A1

公开(公告)日：2019-10-03

申请号：PCT/US2019/019968

申请日：2019-02-28

Applicant: INTEL CORPORATION

Inventor： CHYNOWETH, Michael W. ,  CHABUKSWAR, Rajshree ,  WEISSMANN, Eliezer ,  BRANDT, Jason W. ,  GENDLER, Alexander ,  YASIN, Ahmad ,  KONSOR, Patrick ,  GOHAD, Sneha ,  FREELOVE, William

IPC: G06F1/32 ,  G06F12/1045 ,  G06F11/34

Abstract: In one embodiment, a processor includes one or more cores including a cache memory hierarchy; a performance monitor coupled to the one or more cores, the performance monitor to monitor performance of the one or more cores, the performance monitor to calculate pipeline cost metadata based at least in part on count information associated with the cache memory hierarchy; and a power controller coupled to the performance monitor, the power controller to receive the pipeline cost metadata and determine a low power state for the one or more cores to enter based at least in part on the pipeline cost metadata. Other embodiments are described and claimed.

公开(公告)号：WO2018026527A1

公开(公告)日：2018-02-08

申请号：PCT/US2017/042999

申请日：2017-07-20

Applicant: INTEL CORPORATION

Inventor： WEISSMANN, Eliezer ,  ROSENZWEIG, Nir ,  ROTEM, Efraim ,  BEN-RAPHAEL, Yoav ,  NAVEH, Alon

IPC: G06F1/32 ,  G06F9/50

CPC classification number: G06F1/3287 ,  G06F1/3206 ,  G06F1/3296 ,  Y02D10/171 ,  Y02D10/172 ,  Y02D50/20

Abstract: In one embodiment, a processor includes: a plurality of cores; a power controller including a logic to autonomously demote a first request for at least one core of the plurality of cores to enter a first low power state, to cause the at least one core to enter a second low power state, the first low power state a deeper low power state than the second low power state; and an interface to receive an input from a system software, the input including at least one demotion control parameter, where the logic is to autonomously demote the first request based at least in part on the at least one demotion control parameter. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器包括：多个核心; 功率控制器，所述功率控制器包括逻辑，以自主降级对所述多个核心中的至少一个核心的第一请求以进入第一低功率状态，以使所述至少一个核心进入第二低功率状态，所述第一低功率状态 比第二低功率状态更深的低功率状态; 以及用于接收来自系统软件的输入的接口，所述输入包括至少一个降级控制参数，其中所述逻辑至少部分地基于所述至少一个降级控制参数来自主降级所述第一请求。 描述并要求保护其他实施例。

公开(公告)号：WO2017222690A1

公开(公告)日：2017-12-28

申请号：PCT/US2017/033253

申请日：2017-05-18

Applicant: INTEL CORPORATION

Inventor： WEISSMANN, Eliezer ,  ROTEM, Efraim ,  AIZIK, Yoni ,  RAJWAN, Doron ,  LEIBOVICH, Gal ,  SHULMAN, Nadav ,  ABU SALAH, Hisham

IPC: G06F1/32

CPC classification number: G06F1/3287 ,  G06F1/266 ,  G06F13/24 ,  Y02D10/14

Abstract: In one embodiment, a processor includes a plurality of cores and a power controller including a first logic, responsive to a determination that the processor resided in a forced idle state for less than a threshold duration, to update a first counter and, responsive to a value of the first counter that exceeds a control threshold, prevent the processor from entry into the forced idle state. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器包括多个核心和功率控制器，功率控制器包括第一逻辑，响应于确定处理器处于强制空闲状态少于阈值持续时间，以更新 第一计数器，并且响应于超过控制阈值的第一计数器的值，防止处理器进入强制空闲状态。 描述并要求保护其他实施例。

公开(公告)号：WO2014105174A1

公开(公告)日：2014-07-03

申请号：PCT/US2013/047700

申请日：2013-06-25

Applicant: INTEL CORPORATION ,  NARVAEZ, Paolo ,  SRINIVASA, Ganapati, N. ,  GORBATOV, Eugene ,  SUBBAREDDY, Dheeraj, R. ,  NAIK, Mishali ,  NAVEH, Alon ,  PRABHAKARAN, Abirami ,  WEISSMANN, Eliezer ,  KOUFATY, David, A. ,  BRETT, Paul ,  HAHN, Scott, D. ,  HERDRICH, Andrew, J. ,  KHANNA, Gaurav ,  FENGER, Russell, J. ,  BIGBEE, Bryant, E. ,  HENROID, Andrew, D.

Inventor： NARVAEZ, Paolo ,  SRINIVASA, Ganapati, N. ,  GORBATOV, Eugene ,  SUBBAREDDY, Dheeraj, R. ,  NAIK, Mishali ,  NAVEH, Alon ,  PRABHAKARAN, Abirami ,  WEISSMANN, Eliezer ,  KOUFATY, David, A. ,  BRETT, Paul ,  HAHN, Scott, D. ,  HERDRICH, Andrew, J. ,  KHANNA, Gaurav ,  FENGER, Russell, J. ,  BIGBEE, Bryant, E. ,  HENROID, Andrew, D.

IPC: G06F9/44

CPC classification number: G06F9/45558 ,  G06F9/3885 ,  G06F9/5077 ,  G06F2009/4557

Abstract: A heterogeneous processor architecture is described. For example, a processor according to one embodiment of the invention comprises: a set of two or more small physical processor cores; at least one large physical processor core having relatively higher performance processing capabilities and relatively higher power usage relative to the small physical processor cores; virtual-to-physical (V-P) mapping logic to expose the set of two or more small physical processor cores to software through a corresponding set of virtual cores and to hide the at least one large physical processor core from the software.

Abstract translation: 描述异构处理器架构。 例如，根据本发明的一个实施例的处理器包括：一组两个或更多个小物理处理器核; 至少一个大型物理处理器核具有相对较高性能的处理能力和相对较小的物理处理器核的相对较高的功率使用; 虚拟到物理（V-P）映射逻辑，以通过相应的一组虚拟核心将两个或更多个小型物理处理器核心的集合暴露给软件，并从软件中隐藏至少一个大型物理处理器核心。

公开(公告)号：WO2014105152A1

公开(公告)日：2014-07-03

申请号：PCT/US2013/046911

申请日：2013-06-20

Applicant: INTEL CORPORATION

Inventor： BEN-KIKI, Oren ,  PARDO, Ilan ,  WEISSMANN, Eliezer

IPC: G06F12/10

CPC classification number: G06F9/3861 ,  G06F9/30054 ,  G06F9/30189 ,  G06F9/3881

Abstract: A processor comprising: execution logic to execute a first thread including an accelerator invocation instruction to invoke an accelerator command; an accelerator to execute an accelerator thread in response to the accelerator command, the accelerator to store state data associated with the accelerator thread in a application memory area in memory, wherein prior to executing the accelerator thread, the accelerator is to lock entries in a translation lookaside buffer (TLB) associated with the accelerator thread to prevent an exception which might otherwise result.

Abstract translation: 一种处理器，包括执行逻辑，以执行包括调用加速器命令的加速器调用指令的第一线程; 加速器，其响应于加速器命令执行加速器线程，加速器，用于将与加速器线程相关联的状态数据存储在存储器中的应用存储器区域中，其中在执行加速器线程之前，加速器将锁定条目转换为 与加速器线程相关联的后备缓冲器（TLB），以防止否则可能导致的异常。

公开(公告)号：WO2014105058A1

公开(公告)日：2014-07-03

申请号：PCT/US2012/072135

申请日：2012-12-28

Applicant: INTEL CORPORATION ,  SUBBAREDDY, Dheeraj R. ,  SRINIVASA, Ganapati N. ,  KOUFATY, David A. ,  HAHN, Scott D. ,  NAIK, Mishali ,  NARVAEZ, Paolo ,  PRABHAKARAN, Abirami ,  GORBATOV, Eugene ,  NAVEH, Alon ,  SODHI, Inder M. ,  WEISSMANN, Eliezer ,  BRETT, Paul ,  KHANNA, Gaurav ,  FENGER, Russell J.

Inventor： SUBBAREDDY, Dheeraj R. ,  SRINIVASA, Ganapati N. ,  KOUFATY, David A. ,  HAHN, Scott D. ,  NAIK, Mishali ,  NARVAEZ, Paolo ,  PRABHAKARAN, Abirami ,  GORBATOV, Eugene ,  NAVEH, Alon ,  SODHI, Inder M. ,  WEISSMANN, Eliezer ,  BRETT, Paul ,  KHANNA, Gaurav ,  FENGER, Russell J.

IPC: G06F9/06 ,  G06F1/32 ,  G06F9/46 ,  G06F9/44

CPC classification number: G06F9/3885 ,  G06F9/5094 ,  Y02D10/22

Abstract: A processor includes multiple physical cores that support multiple logical cores of different core types, where the core types include a big core type and a small core type. A multi-threaded application includes multiple software threads are concurrently executed by a first subset of logical cores in a first time slot. Based on data gathered from monitoring the execution in the first time slot, the processor selects a second subset of logical cores for concurrent execution of the software threads in a second time slot. Each logical core in the second subset has one of the core types that matches the characteristics of one of the software threads.

Abstract translation: 处理器包括多个物理核，其支持不同核心类型的多个逻辑核，其中核心类型包括大型核心类型和小型核心类型。 多线程应用程序包括多个软件线程，由第一时隙中的逻辑核心的第一子集同时执行。 基于从监视第一时隙中的执行收集的数据，处理器在第二时隙中选择用于并行执行软件线程的逻辑核心的第二子集。 第二子集中的每个逻辑核心具有与其中一个软件线程的特征相匹配的核心类型之一。

公开(公告)号：WO2013147887A1

公开(公告)日：2013-10-03

申请号：PCT/US2012/031681

申请日：2012-03-30

Applicant: INTEL CORPORATION ,  RONEN, Ronny ,  WEISSMANN, Eliezer ,  VAITHIANATHAN, Karthikeyan Karthik ,  COHEN, Ehud ,  GINZBURG, Boris

Inventor： RONEN, Ronny ,  WEISSMANN, Eliezer ,  GINZBURG, Boris

IPC: G06F9/06 ,  G06F12/10 ,  G06F15/80

CPC classification number: G06F9/3016 ,  G06F9/30036 ,  G06F9/3851 ,  G06F9/3881 ,  G06F9/461 ,  G06F9/485

Abstract: An apparatus is described having multiple cores, each core having: a) an accelerator; and, b) a general purpose CPU coupled to the accelerator. The general purpose CPU has functional unit logic circuitry to execute an instruction that returns an amount of storage space to store context information of the accelerator.

Abstract translation: 描述了具有多个芯的装置，每个芯具有：a）加速器; 和b）耦合到加速器的通用CPU。 通用CPU具有功能单元逻辑电路，以执行返回一定量的存储空间以存储加速器的上下文信息的指令。

公开(公告)号：WO2013101175A1

公开(公告)日：2013-07-04

申请号：PCT/US2011/068072

申请日：2011-12-30

Applicant: INTEL CORPORATION ,  RONEN, Ronny ,  GINZBURG, Boris ,  WEISSMANN, Eliezer

Inventor： RONEN, Ronny ,  GINZBURG, Boris ,  WEISSMANN, Eliezer

IPC: G06F9/06 ,  G06F9/30 ,  G06F9/44

CPC classification number: G06F11/0724 ,  G06F9/3881 ,  G06F9/4484 ,  G06F9/54 ,  G06F9/542 ,  G06F11/0793 ,  G06F11/1474

Abstract: Some implementations disclosed herein provide techniques and arrangements for a synchronous software interface for a specialized logic engine. The synchronous software interface may receive, from a first core of a plurality of cores, a control block including a transaction for execution by the specialized logic engine. The synchronous software interface may send the control block to the specialized logic engine and wait to receive a confirmation from the specialized logic engine that the transaction was successfully executed.

Abstract translation: 本文中公开的一些实施例提供了用于专用逻辑引擎的同步软件接口的技术和布置。 同步软件接口可以从多个核心的第一核心接收包括专用逻辑引擎执行的事务的控制块。 同步软件接口可以将控制块发送到专用逻辑引擎，并等待从专门的逻辑引擎接收事务成功执行的确认。

公开(公告)号：WO2012125202A1

公开(公告)日：2012-09-20

申请号：PCT/US2011/067968

申请日：2011-12-29

Applicant: INTEL CORPORATION ,  GINZBURG, Boris ,  NATANZON, Esfir ,  OSADCHIY, Ilya ,  RONEN, Ronny ,  WEISSMANN, Eliezer ,  ZACH, Yoav ,  FARRELL, Robert L.

Inventor： GINZBURG, Boris ,  NATANZON, Esfir ,  OSADCHIY, Ilya ,  RONEN, Ronny ,  WEISSMANN, Eliezer ,  ZACH, Yoav ,  FARRELL, Robert L.

IPC: G06F9/06 ,  G06F9/30 ,  G06F13/14 ,  G06F12/08

CPC classification number: G06F12/1027 ,  G06F12/1036 ,  G06F12/109 ,  G06F2212/302 ,  G06F2212/682

Abstract: Page faults arising in a graphics processing unit may be handled by an operating system running on the central processing unit. In some embodiments, this means that unpinned memory can be used for the graphics processing unit. Using unpinned memory in the graphics processing unit may expand the capabilities of the graphics processing unit in some cases.

Abstract translation: 在图形处理单元中出现的页面错误可以由在中央处理单元上运行的操作系统来处理。 在一些实施例中，这意味着未被固定的存储器可以用于图形处理单元。 在图形处理单元中使用未固定的存储器可以在某些情况下扩展图形处理单元的能力。

公开(公告)号：WO2022260731A1

公开(公告)日：2022-12-15

申请号：PCT/US2022/019178

申请日：2022-03-07

Applicant: INTEL CORPORATION

Inventor： KIRUBAKARAN, Deepak Samuel ,  BRAUN, William A. ,  CHABUKSWAR, Rajshree A. ,  DAVIES, Leigh ,  FENGER, Russell J. ,  GENDLER, Alexander ,  RIVAS TOLEDANO, Raoul V. ,  WEISSMANN, Eliezer

IPC: G06F9/48 ,  G06F11/34 ,  G06F11/30

Abstract: Dynamic interrupt steering remaps the handling of interrupts away from processor units executing important workloads. During the operation of a computing system, important workload utilization rates for processor units handling interrupts are determined and those processor units with utilization rates about a threshold value are made unavailable for handling interrupts. Interrupts are dynamically remapped to processor units available for interrupt handling based on processor unit idle state and, in the case of heterogeneous computing systems, processor unit type. Processor units are capable of idle state demotion by, in response to receiving a request to enter into a deep idle state, determining if its interrupt handling rate is greater than a threshold value, and if so, placing itself into a shallower idle state than requested. This avoids the computing system from incurring the expensive idle state exit latency and power costs associated with exiting from a deep idle state.