公开(公告)号：WO2019067126A1

公开(公告)日：2019-04-04

申请号：PCT/US2018/048102

申请日：2018-08-27

Applicant: INTEL CORPORATION

Inventor： GENDLER, Alexander ,  SISTLA, Krishnakanth, V. ,  VARMA, Ankush ,  SZAPIRO, Ariel

IPC: G06F1/32

Abstract: In an embodiment, a processor includes a power control unit, a master processing engine, a set of slave processing engines, and a voltage regulator. The master processing engine is to, in response to a receipt of a change message from the power control unit, control the voltage regulator to adjust a voltage level provided to the master processing engine and the set of slave processing engines. Other embodiments are described and claimed.

公开(公告)号：WO2017222668A1

公开(公告)日：2017-12-28

申请号：PCT/US2017/032108

申请日：2017-05-11

Applicant: INTEL CORPORATION

Inventor： GENDLER, Alexander ,  BEZBROZ, Henrietta

IPC: G06F1/32

CPC classification number: G06F1/3287 ,  G06F9/4418 ,  G06F13/24 ,  Y02D10/171

Abstract: In one embodiment, a processor includes: a plurality of cores, at least some having an advanced programmable interrupt controller (APIC) identifier associated therewith; a plurality of power management agents associated with the plurality of cores; and a power controller to receive an indication of an interrupt and a first APIC identifier and send a wake signal and the first APIC identifier to the plurality of power management agents to determine which of the plurality of cores is associated with the first APIC identifier. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，一种处理器包括：多个核，至少一些核具有与之相关联的高级可编程中断控制器（APIC）标识符; 与所述多个核心相关联的多个功率管理代理; 以及功率控制器，用于接收中断和第一APIC标识符的指示，并向所述多个功率管理代理发送唤醒信号和所述第一APIC标识符，以确定所述多个内核中的哪一个与所述第一APIC标识符相关联。 描述并要求保护其他实施例。

公开(公告)号：WO2022271234A1

公开(公告)日：2022-12-29

申请号：PCT/US2022/021566

申请日：2022-03-23

Applicant: INTEL CORPORATION

Inventor： SHAH, Pritesh P. ,  CHEMUDUPATI, Suresh ,  GENDLER, Alexander ,  HUNT, David ,  MACNAMARA, Christopher M. ,  NATHAN, Ofer ,  PURANDARE, Adwait ,  VARMA, Ankush

IPC: G06F1/3209 ,  G06F1/324 ,  G06F1/3234 ,  G06F1/3228 ,  G06F1/3287 ,  G06F1/3296 ,  G06F9/5094

Abstract: A hardware controller within a core of a processor is described. The hardware controller includes telemetry logic to generate telemetry data that indicates an activity state of the core; core stall detection logic to determine, based on the telemetry data from the telemetry logic, whether the core is in an idle loop state; and a power controller that, in response to the core stall detection logic determining that the core is in the idle loop state, is to decrease a power mode of the core from a first power mode associated with a first set of power settings to a second power mode associated with a second set of power settings.

公开(公告)号：WO2019133172A1

公开(公告)日：2019-07-04

申请号：PCT/US2018/063054

申请日：2018-11-29

Applicant: INTEL CORPORATION

Inventor： WEISSMANN, Eliezer ,  GENDLER, Alexander ,  ROTEM, Efraim ,  COHEN, Moshe ,  MALLICK, Asit K. ,  BRANDT, Jason, W. ,  SUBRAMANIAM, Kameswar ,  FELLMAN, Nathan ,  SHAFI, Hisham

IPC: G06F13/36

Abstract: Processor, method, and system for reducing latency in accessing remote registers is described herein. One embodiment of a processor includes one or more remote registers and remote register access circuitry. The remote register access circuitry is to detect a request from the requestor to access a first register of the one or more remote registers, access to the first register in accordance to the request without the requestor having to wait for completion of the access, and provide a notification accessible to the requestor upon completion of the access to the first register of the one or more remote registers.

公开(公告)号：WO2017218123A1

公开(公告)日：2017-12-21

申请号：PCT/US2017/032718

申请日：2017-05-15

Applicant: INTEL CORPORATION

Inventor： GENDLER, Alexander ,  ROTEM, Efraim ,  ROSENZWEIG, Nir ,  SISTLA, Krishnakanth V. ,  CHOUBAL, Ashish V. ,  VARMA, Ankush

IPC: G06F1/32

Abstract: Apparatuses, methods and storage medium associated with current control for a multicore processor are disclosed herein. In embodiments, a multicore processor may include a plurality of analog current comparators, each analog current comparator to measure current utilization by a corresponding one of the cores of the multicore processor. The multicore processor may include one or more processors, devices, and/or circuitry to cause the cores to individually throttle based on measurements from the corresponding analog current comparators. In some embodiments, a memory device of the multicore processor may store instructions executable to operate a plurality power management agents to determine whether to send throttle requests based on a plurality of histories of the current measurements of the cores, respectively.

Abstract translation: 本文公开了与用于多核处理器的电流控制相关联的设备，方法和存储介质。 在实施例中，多核处理器可以包括多个模拟电流比较器，每个模拟电流比较器用于测量多核处理器的相应一个核的电流利用率。 多核处理器可以包括一个或多个处理器，设备和/或电路，以基于来自相应的模拟电流比较器的测量结果使这些核心单独调节。 在一些实施例中，多核处理器的存储器装置可存储可执行以操作多个功率管理代理以分别基于核心的当前测量的多个历史来确定是否发送节流请求的指令。

公开(公告)号：WO2017105734A1

公开(公告)日：2017-06-22

申请号：PCT/US2016/062175

申请日：2016-11-16

Applicant: INTEL CORPORATION

Inventor： GARG, Vivek ,  GENDLER, Alexander ,  RAMAN, Arvind ,  CHOUBAL, Ashish V. ,  SISTLA, Krishnakanth V. ,  MULLA, Dean ,  DEHAEMER, Eric J. ,  AGRAWAL, Rahul ,  SOTOMAYOR, Guy G.

IPC: G06F9/38

CPC classification number: G06F1/26 ,  G06F1/3243 ,  Y02D10/152

Abstract: In one embodiment, a processor includes cores to execute instructions. At least some of the cores include a telemetry data control logic to send a first telemetry data packet to a power controller according to a stagger schedule to prevent data collisions, and a global alignment counter to count a stagger alignment period. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器包括用于执行指令的核心。 至少一些核心包括遥测数据控制逻辑，用于根据交错时间表将第一遥测数据分组发送到功率控制器以防止数据冲突，以及全局对准计数器对交错对准时间段进行计数。 描述并要求保护其他实施例。

公开(公告)号：WO2022260731A1

公开(公告)日：2022-12-15

申请号：PCT/US2022/019178

申请日：2022-03-07

Applicant: INTEL CORPORATION

Inventor： KIRUBAKARAN, Deepak Samuel ,  BRAUN, William A. ,  CHABUKSWAR, Rajshree A. ,  DAVIES, Leigh ,  FENGER, Russell J. ,  GENDLER, Alexander ,  RIVAS TOLEDANO, Raoul V. ,  WEISSMANN, Eliezer

IPC: G06F9/48 ,  G06F11/34 ,  G06F11/30

Abstract: Dynamic interrupt steering remaps the handling of interrupts away from processor units executing important workloads. During the operation of a computing system, important workload utilization rates for processor units handling interrupts are determined and those processor units with utilization rates about a threshold value are made unavailable for handling interrupts. Interrupts are dynamically remapped to processor units available for interrupt handling based on processor unit idle state and, in the case of heterogeneous computing systems, processor unit type. Processor units are capable of idle state demotion by, in response to receiving a request to enter into a deep idle state, determining if its interrupt handling rate is greater than a threshold value, and if so, placing itself into a shallower idle state than requested. This avoids the computing system from incurring the expensive idle state exit latency and power costs associated with exiting from a deep idle state.

公开(公告)号：WO2020205114A1

公开(公告)日：2020-10-08

申请号：PCT/US2020/020411

申请日：2020-02-28

Applicant: INTEL CORPORATION

Inventor： GENDLER, Alexander ,  AIZIK, Yoni ,  RANEL, Chen ,  MELAMED, Ido ,  VAIBERMAN, Edward

IPC: G06F1/3234 ,  G06F15/78

Abstract: Embodiments include an autonomous core perimeter, configured to save the state of a core of a multi-core processor prior to the processor package being placed into a lowpower state. The autonomous core perimeter of each core is configured to save an image of a microcontroller firmware to an external store if it has not been previously saved by another core, along with the unique working state information of that cores microcontroller. Upon restore, the single microcontroller firmware image is retrieved from the external store and pushed to each core along with each cores unique working state.

公开(公告)号：WO2020197870A1

公开(公告)日：2020-10-01

申请号：PCT/US2020/023278

申请日：2020-03-18

Applicant: INTEL CORPORATION

Inventor： JAMBUR SATHYANARAYANA, Krishnamurthy ,  VALENTINE, Robert ,  GENDLER, Alexander ,  ZOBEL, Shmuel ,  BERGER, Gavri ,  STEINER, Ian M. ,  GUPTA, Nikhil ,  HADAS, Eyal ,  HACHAMO, Edo ,  SUBRAMANIAN, Sumesh

IPC: G06F1/3234 ,  G06F1/3296 ,  G06F1/324

Abstract: In one embodiment, a processor includes a current protection controller to: receive instruction width information and instruction type information associated with one or more instructions stored in an instruction queue prior to execution of the one or more instructions by an execution circuit; determine a power license level for the core based on the corresponding instruction width information and the instruction type information; generate a request for a license for the core corresponding to the power license level; and communicate the request to a power controller when the one or more instructions are non-speculative, and defer communication of the request when at least one of the one or more instructions is speculative. Other embodiments are described and claimed.

公开(公告)号：WO2016209445A1

公开(公告)日：2016-12-29

申请号：PCT/US2016/033626

申请日：2016-05-20

Applicant: INTEL CORPORATION

Inventor： GENDLER, Alexander ,  LURIA, Kosta ,  ALBAHARI, Arye ,  NACHSHON, Ohad

IPC: G06F1/06 ,  G06F1/08 ,  G06F1/26

CPC classification number: G06F1/08 ,  G01R1/203 ,  G01R19/0092 ,  G01R19/16528 ,  G01R19/16533 ,  G06F1/06 ,  G06F1/26

Abstract: A method and apparatus for performing current control for an integrated circuit are described. In one embodiment the apparatus comprises core logic coupled to receive a first current; a clock generator to generate a first clock signal; and a closed loop current controller coupled to the clock generator and coupled to provide a second clock signal to the core logic based on the first clock signal, the current controller to control an amount of the first current received by the core logic by changing the first clock signal to generate the second clock signal.

Abstract translation: 描述用于对集成电路进行电流控制的方法和装置。 在一个实施例中，该装置包括耦合以接收第一电流的核心逻辑; 时钟发生器，用于产生第一时钟信号; 以及闭环电流控制器，其耦合到所述时钟发生器并被耦合以基于所述第一时钟信号向所述核心逻辑提供第二时钟信号，所述电流控制器通过改变所述第一时钟信号来控制由所述核心逻辑接收到的所述第一电流的量 时钟信号以产生第二时钟信号。