公开(公告)号：WO2019040050A1

公开(公告)日：2019-02-28

申请号：PCT/US2017/048059

申请日：2017-08-22

Applicant: INTEL CORPORATION

Inventor： ROTEM, Efraim ,  WEISSMANN, Eliezer ,  RAJWAN, Doron ,  AIZIK, Yoni ,  NATANZON, Esfir ,  ROSENZWEIG, Nir ,  SHULMAN, Nadav ,  PLACKLE, Bart

IPC: G06F1/32 ,  G06F9/50

Abstract: Embodiments include apparatuses, methods, and systems including a power control unit to control different power consumptions by one or more processors to operate different applications. The power control unit may receive power information that may include a priority information for each application to be operated on the one or more processors, determine to control, based on the power information for different applications, different power consumptions by the one or more processors to operate the different applications. Other embodiments may also be described and claimed.

公开(公告)号：WO2017052741A1

公开(公告)日：2017-03-30

申请号：PCT/US2016/043702

申请日：2016-07-22

Applicant: INTEL CORPORATION

Inventor： RAJWAN, Doron ,  WEISSMANN, Eliezer ,  AIZIK, Yoni ,  FEIT, Itai ,  KUZI, Tal ,  ZIV, Tomer ,  SHULMAN, Nadav

IPC: G06F9/48 ,  G06F1/32

CPC classification number: G06F11/3024 ,  G01V11/002 ,  G06F1/3228 ,  G06F1/324 ,  G06F9/5094 ,  G06F11/3058 ,  G06F11/3409 ,  G06F11/3419 ,  G06F11/3452 ,  G06F11/348 ,  G06F2201/88

Abstract: Methods and apparatus relating to techniques for flexible and/or dynamic frequency-related telemetry are described. In an embodiment, logic, coupled to a processor, communicates information to a module. The communicated information includes a duration counter value corresponding to a duration in which an operating characteristic of the processor is controlled. Other embodiments are also disclosed and claimed.

Abstract translation: 描述了与灵活和/或动态频率相关的遥测技术相关的方法和装置。 在一个实施例中，耦合到处理器的逻辑将信息传送到模块。 所传送的信息包括对应于其中控制处理器的操作特性的持续时间的持续时间计数器值。 还公开并要求保护其他实施例。

公开(公告)号：WO2017222690A1

公开(公告)日：2017-12-28

申请号：PCT/US2017/033253

申请日：2017-05-18

Applicant: INTEL CORPORATION

Inventor： WEISSMANN, Eliezer ,  ROTEM, Efraim ,  AIZIK, Yoni ,  RAJWAN, Doron ,  LEIBOVICH, Gal ,  SHULMAN, Nadav ,  ABU SALAH, Hisham

IPC: G06F1/32

CPC classification number: G06F1/3287 ,  G06F1/266 ,  G06F13/24 ,  Y02D10/14

Abstract: In one embodiment, a processor includes a plurality of cores and a power controller including a first logic, responsive to a determination that the processor resided in a forced idle state for less than a threshold duration, to update a first counter and, responsive to a value of the first counter that exceeds a control threshold, prevent the processor from entry into the forced idle state. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器包括多个核心和功率控制器，功率控制器包括第一逻辑，响应于确定处理器处于强制空闲状态少于阈值持续时间，以更新 第一计数器，并且响应于超过控制阈值的第一计数器的值，防止处理器进入强制空闲状态。 描述并要求保护其他实施例。

公开(公告)号：WO2020242991A1

公开(公告)日：2020-12-03

申请号：PCT/US2020/034346

申请日：2020-05-22

Applicant: INTEL CORPORATION

Inventor： RANEL, Chen ,  LAKE, Christopher J. ,  DOSHI, Hem ,  MELAMED, Ido ,  DEGALAHAL, Vijay ,  SABIN, Yevgeni ,  PATEL, Reena ,  BEN-RAPHAEL, Yoav ,  ANGEL, Nimrod ,  ROTEM, Efraim ,  CONRAD, Shaun ,  ZIV, Tomer ,  ROSENZWEIG, Nir ,  NATANZON, Esfir ,  AIZIK, Yoni ,  GIHON, Arik ,  ABITAN, Natanel

IPC: G06F1/3237 ,  G06F1/06

Abstract: Techniques and mechanisms for transparently transitioning an interconnect fabric between a first frequency and a second frequency. In an embodiment, the fabric is coupled to an end point device via an asynchronous device. One or more nodes of the fabric operate in a first clock domain based on a clock signal, while the end point device operates in a different clock domain. Controller circuitry changes a frequency of the clock signal by stalling the clock signal throughout a first period of time which is greater than a duration of three cycles of a lower one of the first frequency or the second frequency. After the first period of time, cycling of the clock signal is provided at the second frequency. In another embodiment, the asynchronous device enables the frequency change without preventing communication with the end point device.

公开(公告)号：WO2019245634A1

公开(公告)日：2019-12-26

申请号：PCT/US2019/026717

申请日：2019-04-10

Applicant: INTEL CORPORATION

Inventor： ABU SALAH, Hisham ,  ROTEM, Efraim ,  WEISSMANN, Eliezer ,  AIZIK, Yoni ,  LEDERMAN, Daniel D.

IPC: G06F1/32

Abstract: In one embodiment, processor includes a first core to execute instructions, and a power controller to control power consumption of the processor. The power controller may include a hardware performance state controller to control a performance state of the first core autonomously to an operating system, and calculate a target operating frequency for the performance state based at least in part on an energy performance preference hint received from the operating system. Other embodiments are described and claimed.

公开(公告)号：WO2020205114A1

公开(公告)日：2020-10-08

申请号：PCT/US2020/020411

申请日：2020-02-28

Applicant: INTEL CORPORATION

Inventor： GENDLER, Alexander ,  AIZIK, Yoni ,  RANEL, Chen ,  MELAMED, Ido ,  VAIBERMAN, Edward

IPC: G06F1/3234 ,  G06F15/78

Abstract: Embodiments include an autonomous core perimeter, configured to save the state of a core of a multi-core processor prior to the processor package being placed into a lowpower state. The autonomous core perimeter of each core is configured to save an image of a microcontroller firmware to an external store if it has not been previously saved by another core, along with the unique working state information of that cores microcontroller. Upon restore, the single microcontroller firmware image is retrieved from the external store and pushed to each core along with each cores unique working state.

公开(公告)号：WO2019005392A1

公开(公告)日：2019-01-03

申请号：PCT/US2018/035042

申请日：2018-05-30

Applicant: INTEL CORPORATION

Inventor： ROTEM, Efraim ,  WEISSMANN, Eliezer ,  RAJWAN, Doron ,  ROSENZWEIG, Nir ,  AIZIK, Yoni

IPC: G06F1/32 ,  G06F11/16

Abstract: In one embodiment, a processor includes a plurality of cores, at least two of which may execute redundantly, a configuration register to store a first synchronization domain indicator to indicate that a first core and a second core are associated with a first synchronization domain, and a power controller having a synchronization circuit to cause a dynamic adjustment to a frequency of at least one of the first and second cores to cause these cores to operate at a common frequency, based at least in part on the first synchronization domain indicator. Other embodiments are described and claimed.

公开(公告)号：WO2016191032A1

公开(公告)日：2016-12-01

申请号：PCT/US2016/029923

申请日：2016-04-29

Applicant: INTEL CORPORATION

Inventor： WEISSMANN, Eliezer ,  ROTEM, Efraim ,  ABU SALAH, Hisham ,  AIZIK, Yoni ,  RAJWAN, Doron ,  ROSENZWEIG, Nir ,  LEIBOVICH, Gal ,  SABIN, Yevgeni ,  LEVY, Shay

IPC: G06F1/32 ,  G06F9/28

CPC classification number: G06F1/3287 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/3296 ,  G06F9/5094 ,  Y02D10/126 ,  Y02D10/152 ,  Y02D10/171 ,  Y02D10/172

Abstract: In one embodiment, a processor comprises: a plurality of processing engines including a first processing engine and a second processing engine to independently execute instructions; and a power controller including a performance state control logic to control a performance state of at least one of the processing engines, and a first logic to determine an average number of active processing engines over a first window, an estimated activity level of the processor for the first window, and adjust at least one of a window length at which the performance state control logic is to perform a performance state determination and at least one activity level threshold, based at least in part on a comparison of the estimated activity level and the average number of active processing engines. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器包括：多个处理引擎，包括独立执行指令的第一处理引擎和第二处理引擎; 以及功率控制器，其包括用于控制所述处理引擎中的至少一个的性能状态的性能状态控制逻辑，以及用于在第一窗口中确定所述主动处理引擎的平均数量的第一逻辑，所述处理器的估计活动级别 并且至少部分地基于所估计的活动级别和所述第一窗口的比较来调整所述性能状态控制逻辑将执行性能状态确定和至少一个活动级别阈值的窗口长度中的至少一个 平均主动处理引擎数。 描述和要求保护其他实施例。

公开(公告)号：WO2014003945A1

公开(公告)日：2014-01-03

申请号：PCT/US2013/043043

申请日：2013-05-29

Applicant: INTEL CORPORATION ,  KAMHI, Gila ,  MORAN, Amit ,  DAVID, Limor ,  AIZIK, Yoni

Inventor： KAMHI, Gila ,  MORAN, Amit ,  DAVID, Limor ,  AIZIK, Yoni

IPC: G06F17/00

CPC classification number: G06F9/455 ,  G06F11/3414 ,  G06F11/3461

Abstract: Methods, apparatuses and storage medium associated with engineering perceptual computing systems that includes user intent modeling are disclosed herewith. In embodiments, one or more storage medium may include instructions configured to enable a computing device to receive a usage model having a plurality of user event/behavior statistics, and to generate a plurality of traces of user events/behaviors over a period of time to form a workload. The generation may be based at least in part on the user event/behavior statistics. The workload may be for input into an emulator configured to emulate a perceptual computing system. Other embodiments may be disclosed or claimed.

Abstract translation: 本文公开了与包括用户意图建模的工程感知计算系统相关联的方法，装置和存储介质。 在实施例中，一个或多个存储介质可以包括被配置为使得计算设备能够接收具有多个用户事件/行为统计信息的使用模型并且在一段时间内生成用户事件/行为的多个痕迹的指令， 形成工作量。 这一代可以至少部分地基于用户事件/行为统计。 工作负载可以用于输入到被配置为模拟感知计算系统的仿真器中。 可以公开或要求保护其他实施例。