公开(公告)号：WO2014105174A1

公开(公告)日：2014-07-03

申请号：PCT/US2013/047700

申请日：2013-06-25

Applicant: INTEL CORPORATION ,  NARVAEZ, Paolo ,  SRINIVASA, Ganapati, N. ,  GORBATOV, Eugene ,  SUBBAREDDY, Dheeraj, R. ,  NAIK, Mishali ,  NAVEH, Alon ,  PRABHAKARAN, Abirami ,  WEISSMANN, Eliezer ,  KOUFATY, David, A. ,  BRETT, Paul ,  HAHN, Scott, D. ,  HERDRICH, Andrew, J. ,  KHANNA, Gaurav ,  FENGER, Russell, J. ,  BIGBEE, Bryant, E. ,  HENROID, Andrew, D.

Inventor： NARVAEZ, Paolo ,  SRINIVASA, Ganapati, N. ,  GORBATOV, Eugene ,  SUBBAREDDY, Dheeraj, R. ,  NAIK, Mishali ,  NAVEH, Alon ,  PRABHAKARAN, Abirami ,  WEISSMANN, Eliezer ,  KOUFATY, David, A. ,  BRETT, Paul ,  HAHN, Scott, D. ,  HERDRICH, Andrew, J. ,  KHANNA, Gaurav ,  FENGER, Russell, J. ,  BIGBEE, Bryant, E. ,  HENROID, Andrew, D.

IPC: G06F9/44

CPC classification number: G06F9/45558 ,  G06F9/3885 ,  G06F9/5077 ,  G06F2009/4557

Abstract: A heterogeneous processor architecture is described. For example, a processor according to one embodiment of the invention comprises: a set of two or more small physical processor cores; at least one large physical processor core having relatively higher performance processing capabilities and relatively higher power usage relative to the small physical processor cores; virtual-to-physical (V-P) mapping logic to expose the set of two or more small physical processor cores to software through a corresponding set of virtual cores and to hide the at least one large physical processor core from the software.

Abstract translation: 描述异构处理器架构。 例如，根据本发明的一个实施例的处理器包括：一组两个或更多个小物理处理器核; 至少一个大型物理处理器核具有相对较高性能的处理能力和相对较小的物理处理器核的相对较高的功率使用; 虚拟到物理（V-P）映射逻辑，以通过相应的一组虚拟核心将两个或更多个小型物理处理器核心的集合暴露给软件，并从软件中隐藏至少一个大型物理处理器核心。

公开(公告)号：WO2014105058A1

公开(公告)日：2014-07-03

申请号：PCT/US2012/072135

申请日：2012-12-28

Applicant: INTEL CORPORATION ,  SUBBAREDDY, Dheeraj R. ,  SRINIVASA, Ganapati N. ,  KOUFATY, David A. ,  HAHN, Scott D. ,  NAIK, Mishali ,  NARVAEZ, Paolo ,  PRABHAKARAN, Abirami ,  GORBATOV, Eugene ,  NAVEH, Alon ,  SODHI, Inder M. ,  WEISSMANN, Eliezer ,  BRETT, Paul ,  KHANNA, Gaurav ,  FENGER, Russell J.

Inventor： SUBBAREDDY, Dheeraj R. ,  SRINIVASA, Ganapati N. ,  KOUFATY, David A. ,  HAHN, Scott D. ,  NAIK, Mishali ,  NARVAEZ, Paolo ,  PRABHAKARAN, Abirami ,  GORBATOV, Eugene ,  NAVEH, Alon ,  SODHI, Inder M. ,  WEISSMANN, Eliezer ,  BRETT, Paul ,  KHANNA, Gaurav ,  FENGER, Russell J.

IPC: G06F9/06 ,  G06F1/32 ,  G06F9/46 ,  G06F9/44

CPC classification number: G06F9/3885 ,  G06F9/5094 ,  Y02D10/22

Abstract: A processor includes multiple physical cores that support multiple logical cores of different core types, where the core types include a big core type and a small core type. A multi-threaded application includes multiple software threads are concurrently executed by a first subset of logical cores in a first time slot. Based on data gathered from monitoring the execution in the first time slot, the processor selects a second subset of logical cores for concurrent execution of the software threads in a second time slot. Each logical core in the second subset has one of the core types that matches the characteristics of one of the software threads.

Abstract translation: 处理器包括多个物理核，其支持不同核心类型的多个逻辑核，其中核心类型包括大型核心类型和小型核心类型。 多线程应用程序包括多个软件线程，由第一时隙中的逻辑核心的第一子集同时执行。 基于从监视第一时隙中的执行收集的数据，处理器在第二时隙中选择用于并行执行软件线程的逻辑核心的第二子集。 第二子集中的每个逻辑核心具有与其中一个软件线程的特征相匹配的核心类型之一。

公开(公告)号：WO2019133052A1

公开(公告)日：2019-07-04

申请号：PCT/US2018/040390

申请日：2018-06-29

Applicant: YANG, Shao-Wen ,  CHEN, Yen-Kuang ,  ALTARAWNEH, Ragaad Mohammed Irsehid ,  MUNOZ CHIABRANDO, Juan Pablo ,  CHIN, Siew Wen ,  DATTA, Kushal ,  DULLOOR, Subramanya R. ,  ZAMORA ESQUIVEL, Julio C. ,  FLOREZ CHOQUE, Omar Ulises ,  GUPTA, Vishakha ,  HAHN, Scott D. ,  ILLIKKAL, Rameshkumar ,  JAIN, Nilesh Kumar ,  KAMAROL, Siti Khairuni Amalina ,  KESHAVAMURTHY, Anil S. ,  LAU, Heng Kar ,  LEFMAN, Jonathan A. ,  LIAO, Yiting ,  MILLSAP, Michael G. ,  NDIOUR, Ibrahima J. ,  REMIS, Luis Carlos Maria ,  SANJAY, Addicam V. ,  SARWAR, Usman ,  SCHOOLER, Eve M. ,  SMITH, Ned M. ,  SOMAYAZULU, Vallabhajosyula S. ,  STRONG, Christina R. ,  TICKOO, Omesh ,  VARADARAJAN, Srenivas ,  VARGAS, Jesús A. Cruz ,  MOUSTAFA, Hassnaa ,  RAGHUNATH, Arun ,  BARTFAI-WALCOTT, Katalin Klara ,  HYDE, Maruti Gupta ,  VEMBAR, Deepak S. ,  MCCARTHY, Jessica

Inventor： YANG, Shao-Wen ,  CHEN, Yen-Kuang ,  ALTARAWNEH, Ragaad Mohammed Irsehid ,  MUNOZ CHIABRANDO, Juan Pablo ,  CHIN, Siew Wen ,  DATTA, Kushal ,  DULLOOR, Subramanya R. ,  ZAMORA ESQUIVEL, Julio C. ,  FLOREZ CHOQUE, Omar Ulises ,  GUPTA, Vishakha ,  HAHN, Scott D. ,  ILLIKKAL, Rameshkumar ,  JAIN, Nilesh Kumar ,  KAMAROL, Siti Khairuni Amalina ,  KESHAVAMURTHY, Anil S. ,  LAU, Heng Kar ,  LEFMAN, Jonathan A. ,  LIAO, Yiting ,  MILLSAP, Michael G. ,  NDIOUR, Ibrahima J. ,  REMIS, Luis Carlos Maria ,  SANJAY, Addicam V. ,  SARWAR, Usman ,  SCHOOLER, Eve M. ,  SMITH, Ned M. ,  SOMAYAZULU, Vallabhajosyula S. ,  STRONG, Christina R. ,  TICKOO, Omesh ,  VARADARAJAN, Srenivas ,  VARGAS, Jesús A. Cruz ,  MOUSTAFA, Hassnaa ,  RAGHUNATH, Arun ,  BARTFAI-WALCOTT, Katalin Klara ,  HYDE, Maruti Gupta ,  VEMBAR, Deepak S. ,  MCCARTHY, Jessica

IPC: G06T7/11 ,  G06T1/00

Abstract: In one embodiment, an apparatus comprises a processor to: identify a workload comprising a plurality of tasks; generate a workload graph based on the workload, wherein the workload graph comprises information associated with the plurality of tasks; identify a device connectivity graph, wherein the device connectivity graph comprises device connectivity information associated with a plurality of processing devices; identify a privacy policy associated with the workload; identify privacy level information associated with the plurality of processing devices; identify a privacy constraint based on the privacy policy and the privacy level information; and determine a workload schedule, wherein the workload schedule comprises a mapping of the workload onto the plurality of processing devices, and wherein the workload schedule is determined based on the privacy constraint, the workload graph, and the device connectivity graph. The apparatus further comprises a communication interface to send the workload schedule to the plurality of processing devices.

公开(公告)号：WO2013162589A1

公开(公告)日：2013-10-31

申请号：PCT/US2012/035339

申请日：2012-04-27

Applicant: INTEL CORPORATION ,  NAVEH, Alon ,  YOSEF, Yuval ,  WEISSMANN, Eliezer ,  AGGARWAL, Anil ,  ROTEM, Efraim ,  MENDELSON, Avi ,  RONEN, Ronny ,  GINZBURG, Boris ,  MISHAELI, Michael ,  HAHN, Scott D. ,  KOUFATY, David A. ,  SRINIVASA, Ganapati ,  THERIEN, Guy

Inventor： NAVEH, Alon ,  YOSEF, Yuval ,  WEISSMANN, Eliezer ,  AGGARWAL, Anil ,  ROTEM, Efraim ,  MENDELSON, Avi ,  RONEN, Ronny ,  GINZBURG, Boris ,  MISHAELI, Michael ,  HAHN, Scott D. ,  KOUFATY, David A. ,  SRINIVASA, Ganapati ,  THERIEN, Guy

IPC: G06F9/46 ,  G06F9/22 ,  G06F15/80

CPC classification number: G06F9/30145 ,  G06F9/4856 ,  G06F9/5094 ,  G06F2209/5018 ,  Y02D10/22 ,  Y02D10/24 ,  Y02D10/32

Abstract: In one embodiment, the present invention includes a multicore processor having first and second cores to independently execute instructions, the first core visible to an operating system (OS) and the second core transparent to the OS and heterogeneous from the first core. A task controller, which may be included in or coupled to the multicore processor, can cause dynamic migration of a first process scheduled by the OS to the first core to the second core transparently to the OS. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括具有第一和第二核心以独立执行指令的多核处理器，操作系统（OS）可见的第一核心和对OS可透明的第二核心，并且与第一核心不同。 可以包括在多核处理器中或耦合到多核处理器的任务控制器可以使由OS所安排的第一进程到OS的第一核心到第二核心的动态迁移到第二核心。 描述和要求保护其他实施例。

公开(公告)号：WO2014105197A1

公开(公告)日：2014-07-03

申请号：PCT/US2013/048352

申请日：2013-06-27

Applicant: INTEL CORPORATION ,  NARVAEZ, Paolo ,  SRINIVASA, Ganapati, N. ,  GORBATOV, Eugene ,  SUBBAREDDY, Dheeraj, R. ,  NAIK, Mishali ,  NAVEH, Alon ,  PRABHAKARAN, Abirami ,  WEISSMANN, Eliezer ,  KOUFATY, David, A. ,  BRETT, Paul ,  HAHN, Scott, D. ,  HERDRICH, Andrew, J. ,  SODHI, Inder, M. ,  KHANNA, Gaurv ,  FENGER, Russel, J. ,  BIGBEE, Bryant, E. ,  HENROID, Andrew D.

Inventor： NARVAEZ, Paolo ,  SRINIVASA, Ganapati, N. ,  GORBATOV, Eugene ,  SUBBAREDDY, Dheeraj, R. ,  NAIK, Mishali ,  NAVEH, Alon ,  PRABHAKARAN, Abirami ,  WEISSMANN, Eliezer ,  KOUFATY, David, A. ,  BRETT, Paul ,  HAHN, Scott, D. ,  HERDRICH, Andrew, J. ,  SODHI, Inder, M. ,  KHANNA, Gaurv ,  FENGER, Russel, J. ,  BIGBEE, Bryant, E. ,  HENROID, Andrew D.

IPC: G06F9/38 ,  G06F9/46

CPC classification number: G06F9/3891

Abstract: A heterogeneous processor architecture is described. For example, a processor according to one embodiment of the invention comprises: a set of large physical processor cores; a set of small physical processor cores having relatively lower performance processing capabilities and relatively lower power usage relative to the large physical processor cores; virtual-to-physical (V-P) mapping logic to expose the set of large physical processor cores to software through a corresponding set of virtual cores and to hide the set of small physical processor core from the software.

Abstract translation: 描述异构处理器架构。 例如，根据本发明的一个实施例的处理器包括：一组大的物理处理器核心; 一组具有相对较低性能处理能力的小物理处理器核和相对于大型物理处理器核的相对较低的功率使用; 虚拟到物理（V-P）映射逻辑，以通过相应的一组虚拟核心将大型物理处理器核心集合暴露给软件，并从该软件中隐藏小型物理处理器核心集。

公开(公告)号：WO2014105145A1

公开(公告)日：2014-07-03

申请号：PCT/US2013/046634

申请日：2013-06-19

Applicant: INTEL CORPORATION ,  NARVAEZ, Paolo ,  SRINIVASA, Ganapati N. ,  GORBATOV, Eugene ,  SUBBAREDDY, Dheeraj R. ,  NAIK, Mishali ,  NAVEH, Alon ,  PRABHAKARAN, Abirami ,  WEISSMANN, Eliezer ,  KOUFATY, David A. ,  BRETT, Paul ,  HAHN, Scott D. ,  HERDRICH, Andrew J. ,  IYER, Ravishankar ,  CHITLUR, Nagabhushan ,  SODHI, Inder M. ,  KHANNA, Gaurav ,  FENGER, Russell J.

Inventor： NARVAEZ, Paolo ,  SRINIVASA, Ganapati N. ,  GORBATOV, Eugene ,  SUBBAREDDY, Dheeraj R. ,  NAIK, Mishali ,  NAVEH, Alon ,  PRABHAKARAN, Abirami ,  WEISSMANN, Eliezer ,  KOUFATY, David A. ,  BRETT, Paul ,  HAHN, Scott D. ,  HERDRICH, Andrew J. ,  IYER, Ravishankar ,  CHITLUR, Nagabhushan ,  SODHI, Inder M. ,  KHANNA, Gaurav ,  FENGER, Russell J.

IPC: G06F9/28 ,  G06F9/38 ,  G06F9/46

CPC classification number: G06F9/5044 ,  G06F9/45533 ,  G06F9/5077 ,  G06F9/5094 ,  G06F15/80 ,  Y02D10/22

Abstract: A heterogeneous processor architecture is described. For example, a processor according to one embodiment of the invention comprises: a first set of one or more physical processor cores having first processing characteristics; a second set of one or more physical processor cores having second processing characteristics different from the first processing characteristics; virtual-to-physical (V-P) mapping logic to expose a plurality of virtual processors to software, the plurality of virtual processors to appear to the software as a plurality of homogeneous processor cores, the software to allocate threads to the virtual processors as if the virtual processors were homogeneous processor cores; wherein the V-P mapping logic is to map each virtual processor to a physical processor within the first set of physical processor cores or the second set of physical processor cores such that a thread allocated to a first virtual processor by software is executed by a physical processor mapped to the first virtual processor from the first set or the second set of physical processors.

Abstract translation: 描述异构处理器架构。 例如，根据本发明的一个实施例的处理器包括：具有第一处理特性的一个或多个物理处理器核心的第一组; 具有不同于所述第一处理特性的第二处理特性的第二组一个或多个物理处理器核; 虚拟到物理（VP）映射逻辑，以将多个虚拟处理器暴露给软件，所述多个虚拟处理器将软件呈现为多个同构的处理器核，所述软件将线程分配给虚拟处理器，如同 虚拟处理器是同类处理器核心; 其中所述VP映射逻辑将每个虚拟处理器映射到所述第一物理处理器核心集合或所述第二物理处理器核心集合内的物理处理器，使得通过软件分配给第一虚拟处理器的线程由物理处理器映射执行 从第一组或第二组物理处理器到第一虚拟处理器。

公开(公告)号：WO2013101139A1

公开(公告)日：2013-07-04

申请号：PCT/US2011/068008

申请日：2011-12-30

Applicant: INTEL CORPORATION ,  GINZBURG, Boris ,  OSADCHIY, Ilya ,  RONEN, Ronny ,  WEISSMANN, Eliezer ,  MISHAELI, Michael ,  NAVEH, Alon ,  KOUFATY, David A. ,  HAHN, Scott D. ,  LI, Tong ,  MENDLESON, Avi ,  GORBATOV, Eugene ,  ABU-SALAH, Hisham ,  SUBBAREDDY, Dheeraj R. ,  NARVAEZ, Paolo ,  JALEEL, Aamer ,  ROTEM, Efraim ,  YOSEF, Yuval ,  AGGARWAL, Anil ,  VAN CRAEYNEST, Kenzo

Inventor： GINZBURG, Boris ,  OSADCHIY, Ilya ,  RONEN, Ronny ,  WEISSMANN, Eliezer ,  MISHAELI, Michael ,  NAVEH, Alon ,  KOUFATY, David A. ,  HAHN, Scott D. ,  LI, Tong ,  MENDLESON, Avi ,  GORBATOV, Eugene ,  ABU-SALAH, Hisham ,  SUBBAREDDY, Dheeraj R. ,  NARVAEZ, Paolo ,  JALEEL, Aamer ,  ROTEM, Efraim ,  YOSEF, Yuval ,  AGGARWAL, Anil ,  VAN CRAEYNEST, Kenzo

IPC: G06F15/80 ,  G06F9/22

CPC classification number: G06F9/4881 ,  G06F9/30101 ,  G06F9/4856 ,  G06F15/7807 ,  Y02D10/12 ,  Y02D10/13 ,  Y02D10/24 ,  Y02D10/32

Abstract: In one embodiment, the present invention includes a multicore processor with first and second groups of cores. The second group can be of a different instruction set architecture (ISA) than the first group or of the same ISA set but having different power and performance support level, and is transparent to an operating system (OS). The processor further includes a migration unit that handles migration requests for a number of different scenarios and causes a context switch to dynamically migrate a process from the second core to a first core of the first group. This dynamic hardware-based context switch can be transparent to the OS. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括具有第一和第二组核心的多核处理器。 第二组可以是不同于第一组或同一ISA组但具有不同功率和性能支持级别的指令集架构（ISA），并且对于操作系统（OS）是透明的。 处理器还包括迁移单元，其处理针对多个不同场景的迁移请求，并使上下文切换将进程从第二核心动态地迁移到第一组的第一核心。 这种基于动态硬件的上下文切换对于操作系统可以是透明的。 描述和要求保护其他实施例。