公开(公告)号：WO0242917A3

公开(公告)日：2002-11-14

申请号：PCT/GB0105138

申请日：2001-11-21

Applicant: ASPEX TECHNOLOGY LTD ,  WHITAKER MARTIN

Inventor： WHITAKER MARTIN

IPC: G06F13/38 ,  G06F13/42 ,  G06F13/40

CPC classification number: G06F13/4226

Abstract: A method of broadcasting data to multiple targets across a systembus (2), such as the peripheral component interconnect. (PCI) bus, that does not normally support broadcast transfers wherein one target (3) respnds to the bus transaction (20, 24, 28) and the remaining targets (4, 5) listen in (snoop) on the bus transaction to receive data from the system bus (2), the method comprising theresponding target (3) stalling (38) or slowing down the bus transaction, or forcing the re-sending of already transmitted data, when any of the listening (snooping) targets (4, 5) communicate (32) to the responding target (3) that they are temporarily unable to accept the data on the bus.

Abstract translation: 通过系统总线（2）（例如外围组件互连）向多个目标广播数据的方法。 （PCI）总线，其通常不支持广播传输，其中一个目标（3）响应于总线事务（20,24,28），并且剩余的目标（4,5）在总线事务上监听（窥探）以接收 来自系统总线（2）的数据，包括对应目标（3）停止（38）或减慢总线事务的方法，或强制重发已经发送的数据，当任何侦听（侦听）目标（4 ，5）将响应目标（3）通信（32），使其暂时不能接受总线上的数据。

公开(公告)号：WO02042917A2

公开(公告)日：2002-05-30

申请号：PCT/GB2001/005138

申请日：2001-11-21

IPC: G06F13/38 ,  G06F13/42 ,  G06F13/00

CPC classification number: G06F13/4226

Abstract: A method of broadcasting data to multiple targets across a systembus (2), such as the peripheral component interconnect. (PCI) bus, that does not normally support broadcast transfers wherein one target (3) respnds to the bus transaction (20, 24, 28) and the remaining targets (4, 5) listen in (snoop) on the bus transaction to receive data from the system bus (2), the method comprising theresponding target (3) stalling (38) or slowing down the bus transaction, or forcing the re-sending of already transmitted data, when any of the listening (snooping) targets (4, 5) communicate (32) to the responding target (3) that they are temporarily unable to accept the data on the bus.

Abstract translation: 通过系统总线（2）（例如外围组件互连）向多个目标广播数据的方法。 （PCI）总线，其通常不支持广播传输，其中一个目标（3）响应于总线事务（20,24,28），并且剩余的目标（4,5）在总线事务上监听（窥探）以接收 来自系统总线（2）的数据，包括对应目标（3）停止（38）或减慢总线事务的方法，或强制重发已经发送的数据，当任何侦听（侦听）目标（4 ，5）将响应目标（3）通信（32），使其暂时不能接受总线上的数据。

公开(公告)号：WO01075618A2

公开(公告)日：2001-10-11

申请号：PCT/US2001/009907

申请日：2001-03-28

IPC: G06F13/42 ,  G06F13/00

CPC classification number: G06F13/4226

Abstract: An interface protocol for transmitting variable-sized packets between a host system and a storage device. The protocol supports a plurality of signals for transmitting data between the host system and the storage device. One or more address signals indicate whether the packet includes command, data, or status information. An enable signal indicates when the packets may be transmitted to and from the storage device. Read and write strobe signals are also included to allow the host to request data from and transmit data to the storage device. The protocol includes an extensible command set which includes a function code, one or more interrupt requests, and signals to indicate when the storage device is busy, when the storage device is ready to transfer data, when the storage device is ready to receive bytes from a command packet, when the storage device is ready to receive or transmit a data block, and when the storage device is ready to transmit status bytes.

Abstract translation: 一种用于在主机系统和存储设备之间传输可变大小的分组的接口协议。 该协议支持用于在主机系统和存储设备之间传输数据的多个信号。 一个或多个地址信号指示分组是否包括命令，数据或状态信息。 启用信号指示何时可以将数据包传输到存储设备和从存储设备发送。 还包括读取和写入选通信号，以允许主机向存储设备请求数据和传输数据。 该协议包括可扩展命令集，其包括功能码，一个或多个中断请求，以及当存储设备准备好传输数据时，当存储设备正在忙时指示的信号，当存储设备准备好接收字节时 当存储设备准备好接收或发送数据块时，以及当存储设备准备好发送状态字节时的命令分组。

公开(公告)号：WO99015980A1

公开(公告)日：1999-04-01

申请号：PCT/US1998/019512

申请日：1998-09-17

IPC: G06F13/42 ,  G06F13/14

CPC classification number: G06F13/4226

Abstract: A system and method for sending device specific data in a bus transaction. A device configurable field is preallocated in a packet sent by the sending device (215) to a receiving device (220). The sending device (215) can configure the data to be stored in the device configurable field. Upon receipt of the packet, the receiving device (220) generates a response packet in which the contents of the device configurable field is simply copied into a corresponding field in the response packet.

Abstract translation: 一种用于在总线事务中发送设备特定数据的系统和方法。 将设备可配置字段预分配在由发送设备（215）发送到接收设备（220）的分组中。 发送设备（215）可以将要存储的数据配置在设备可配置字段中。 在接收到分组时，接收设备（220）产生响应分组，其中设备可配置字段的内容被简单地复制到响应分组中的相应字段中。

公开(公告)号：WO1997050040A2

公开(公告)日：1997-12-31

申请号：PCT/DE1997001219

申请日：1997-06-16

Applicant: SIEMENS AKTIENGESELLSCHAFT ,  OBERLÄNDER, Klaus ,  PFAB, Stefan

Inventor： SIEMENS AKTIENGESELLSCHAFT

IPC: G06F13/42

CPC classification number: G06F13/4226 ,  G06F15/7842 ,  H01R4/2433 ,  H01R13/512 ,  H01R13/565 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

Abstract: A microprocessor device has an arithmetic unit (CPU) which converts the commands stored in a program storage for controlling the various elements of the microprocessor into arithmetic and/or logic operations, and a data and/or control bus (10, 11) for transmitting data and for accessing CPU-internal and/or peripheral-bound special function registers (18) associated to the arithmetic unit. A coherent memory block (24) with memory cells (31a to 31h) of the random access type (RAM is associated by the data and/or control bus (10, 11) to the arithmetic unit. The memory block (24) has its own address decoding and bus driving circuit, a first storage area which can be used or accessed at will and a second directly addressable storage area bound to the peripheral units. A release device (26) associated to the memory block locks or releases the transmission of data from the second storage area to the data and/or control bus (10, 11).

Abstract translation: 本发明涉及一种具有算术逻辑单元（CPU），其中存储在程序存储器命令中的数据，用于控制的算术和/或逻辑运算的形式，微处理器的各种组件中实现，数据和/或控制总线的微处理器装置（10 ，11）（用于数据传输以及用于访问CPU内部和/或外周结合的特殊功能寄存器18），其被分配给该算术单元。 所述计算单元是由所述数据和/或控制线（10，11）是被分配的存储器（24），其具有存储器的随机存取类型（RAM）的小区（31a至31H）的连续块，它有自己的地址解码器和总线驱动器电路的装置，和第一 可用根据需要或具有可访问的存储器区域和第二，外周未结合的和直接寻址存储器区域，其中，所述存储器块包括释放装置（26）与数据内容上的数据和/或控制线（10，11，其输出从所述第二存储区域相关联的 ）锁或释放。

公开(公告)号：WO1993024887A1

公开(公告)日：1993-12-09

申请号：PCT/US1993004810

申请日：1993-05-20

Applicant: NATIONAL INSTRUMENTS CORPORATION

Inventor： NATIONAL INSTRUMENTS CORPORATION ,  THOMSON, Andrew, C. ,  ODOM, Brian, Keith ,  BUTLER, C., Paul ,  JABLIN, Michael, G. ,  NOWLIN, William, C., Jr. ,  CANIK, Robert, W.

IPC: G06F13/00

CPC classification number: G06F13/4226

Abstract: A modified IEEE 488.1 bus (104) interface (100-A, 100-B) increases, by as much as a factor of eight, the rate at which inter-instrument data transfers can be performed. The bus interface state machines (142, 144, 146, 148, 150, 160) presented in the ANSI/IEEE Std 488.1-1987 have been modified so that if all the devices (106) involved in a particular date transfer are equipped to handle high speed data transfers, then a modified data transmission methodology is used so as to enable multiline messages to be transmitted at a higher speed than would otherwise be possible. If any of the devices (106) involved in a particular data transfer does not have an interface equipped to handle high speed data transfers, this condition is automatically detected by the other interfaces with high speed capability, and then the standard data transmission methodology is used. The high speed data transmission mode is totally transparent to the controller (102, 120) software in that it does not require any changes to the controller (102, 120) software nor to the device drivers and device (106) application programs.

Abstract translation: 经过修改的IEEE 488.1总线（104）接口（100-A，100-B）可以增加多达八分之一的能够执行跨仪器数据传输的速率。 在ANSI / IEEE标准488.1-1987中呈现的总线接口状态机（142,144,146,148,150,160）已被修改，使得如果参与特定日期传送的所有设备（106）被配备为处理 高速数据传输，则使用经修改的数据传输方法，以便能够以比其它方式更高的速度发送多行消息。 如果涉及特定数据传输的任何设备（106）没有配备处理高速数据传输的接口，则该条件由具有高速能力的其他接口自动检测，然后使用标准数据传输方法 。 高速数据传输模式对于控制器（102,120）软件是完全透明的，因为它不需要对控制器（102,120）软件以及设备驱动器和设备（106）应用程序的任何改变。

公开(公告)号：WO2017112529A1

公开(公告)日：2017-06-29

申请号：PCT/US2016/067046

申请日：2016-12-19

Applicant: INTEL CORPORATION

Inventor： CHELLAPPAN, Satheesh ,  ZHANG, Chunyu

IPC: G06F13/36

CPC classification number: G06F13/37 ,  G06F1/12 ,  G06F1/26 ,  G06F13/4226

Abstract: In a system where multiple controllers share a link interface but are not all (1) compatible with the same configuration of the physical layer or (2) using the same clocking, a configuration arbitration subsystem intercepts, organizes, and re-clocks configuration-access requests from the various controller agents. Priorities are assigned according to stored policies. The configuration arbiter grants configuration access to the top-priority agent, synchronizing the agent's message with the arbiter's clock. Lower-priority agents' messages are stored in command queues until they ascend to top priority. Besides preventing timing conflicts and streamlining the coordination of clocks, the configuration arbiter may provide access to physical-layer registers beyond the controllers' built-in capabilities to further optimize configuration.

Abstract translation: 在多个控制器共享链路接口但并非全部（1）与物理层的相同配置兼容或（2）使用相同时钟的系统中，配置仲裁子系统拦截，组织 ，并重新记录来自各种控制器代理的配置访问请求。 优先级根据存储的策略进行分配。 配置仲裁器授予对最高优先级代理的配置访问权限，将代理的消息与仲裁器的时钟同步。 低优先级代理的消息存储在命令队列中，直到它们升至最高优先级。 除了防止时序冲突和简化时钟协调之外，配置仲裁器还可以提供对控制器内置功能以外的物理层寄存器的访问，以进一步优化配置。

公开(公告)号：WO2016190915A2

公开(公告)日：2016-12-01

申请号：PCT/US2016/014863

申请日：2016-01-26

Applicant: SPIRE GLOBAL, INC.

Inventor： CAPPAERT, Jeroen ,  TRUTNA, Jesse ,  SHRAKE, Nicholas

IPC: G06F13/42 ,  G06F13/40

CPC classification number: G06F13/4282 ,  G06F13/4022 ,  G06F13/4226 ,  G06F13/4295 ,  H04B7/18515 ,  Y02D10/14 ,  Y02D10/151

Abstract: A cubesat communications system includes an on-board computer implemented on a hardware platform. The on-board computer may include a system on module having a processor and a memory storing "boot" information. The on-board computer may also include a plurality of hardware interfaces implemented on the hardware platform to facilitate communication between the processor and a plurality of peripherals external to the on-board computer. The on-board computer may have a backplane having a plurality of connectors connecting the processor to the peripherals.

Abstract translation: 立体声通信系统包括在硬件平台上实现的车载计算机。 车载计算机可以包括具有处理器的模块上的系统和存储“引导”信息的存储器。 车载计算机还可以包括在硬件平台上实现的多个硬件接口，以便于处理器与车载计算机外部的多个外围设备之间的通信。 车载计算机可以具有背板，其具有将处理器连接到外围设备的多个连接器。

公开(公告)号：WO2006035410A3

公开(公告)日：2006-07-27

申请号：PCT/IB2005053207

申请日：2005-09-28

Applicant: KONINKL PHILIPS ELECTRONICS NV ,  PONTIUS TIMOTHY A ,  ROEVER JENS

Inventor： PONTIUS TIMOTHY A ,  ROEVER JENS

IPC: G06F13/42

CPC classification number: G06F13/4226

Abstract: A data communication arrangement permits efficient data transfer between a controller module (102) and multiple target modules (104) using a two-phase protocol. The controller module (102) and the target modules (104) can each reside in separate clock domains. Consistent with one example embodiment, a data communication arrangement includes a plurality of target modules (104), and a first XOR tree (110) arranged to provide a first data integrity-indicating signal (111) and to respond to a respective second data integrity­indicating signal (108) from each of the target modules (104). A second XOR tree (112) is arranged to provide a first data bus (114) and to respond to a respective second data bus (106) from each of the target modules (104). Also, a controller module (102) is used to determine availability of data on the first data bus (114) in response to the first data integrity-indicating signal (111).

Abstract translation: 数据通信布置允许使用两阶段协议在控制器模块（102）和多个目标模块（104）之间进行有效的数据传输。 控制器模块（102）和目标模块（104）可以分别驻留在分离的时钟域中。 根据一个示例实施例，数据通信装置包括多个目标模块（104）和第一XOR树（110），第一XOR树（110）被布置为提供第一数据完整性指示信号（111）并响应相应的第二数据完整性指示 信号（108）来自每个目标模块（104）。 第二XOR树（112）被布置为提供第一数据总线（114）并且响应于来自每个目标模块（104）的相应的第二数据总线（106）。 而且，响应于第一数据完整性指示信号（111），使用控制器模块（102）来确定第一数据总线（114）上的数据的可用性。

公开(公告)号：WO2006035410A2

公开(公告)日：2006-04-06

申请号：PCT/IB2005/053207

申请日：2005-09-28

Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V. ,  PONTIUS, Timothy A. ,  ROEVER, Jens

Inventor： PONTIUS, Timothy A. ,  ROEVER, Jens

IPC: G06F13/42

CPC classification number: G06F13/4226

Abstract: A data communication arrangement permits efficient data transfer between a controller module (102) and multiple target modules (104) using a two-phase protocol. The controller module (102) and the target modules (104) can each reside in separate clock domains. Consistent with one example embodiment, a data communication arrangement includes a plurality of target modules (104), and a first XOR tree (110) arranged to provide a first data integrity-indicating signal (111) and to respond to a respective second data integrity­indicating signal (108) from each of the target modules (104). A second XOR tree (112) is arranged to provide a first data bus (114) and to respond to a respective second data bus (106) from each of the target modules (104). Also, a controller module (102) is used to determine availability of data on the first data bus (114) in response to the first data integrity-indicating signal (111).

Abstract translation: 数据通信装置允许使用两相协议在控制器模块（102）和多个目标模块（104）之间进行有效的数据传输。 控制器模块（102）和目标模块（104）可以各自驻留在单独的时钟域中。 与一个示例性实施例一致，数据通信装置包括多个目标模块（104）和被布置为提供第一数据完整性指示信号（111）并且响应相应的第二数据完整性指示的第一异或树（110） 来自每个目标模块（104）的信号（108）。 第二异或树（112）被布置成提供第一数据总线（114）并且从每个目标模块（104）响应相应的第二数据总线（106）。 此外，控制器模块（102）用于响应于第一数据完整性指示信号（111）来确定第一数据总线（114）上的数据的可用性。