公开(公告)号：WO2019139738A1

公开(公告)日：2019-07-18

申请号：PCT/US2018/066102

申请日：2018-12-18

Applicant: MICROSOFT TECHNOLOGY LICENSING, LLC

Inventor： RAGHUNATH, Narasimhan ,  GREENLAY, Scott, A. ,  HOGLE, Francis, Miland, IV ,  SU, Fei ,  HODGES, Austin, B. ,  KAZA, Akhilesh

IPC: G06F13/10 ,  G06F9/4401

CPC classification number: G06F9/4411 ,  G06F3/0601 ,  G06F13/102 ,  G06F13/385 ,  G06F13/4226

Abstract: Methods, systems, and computer program products are described herein an extensible input stack for processing input device data received from a plurality of different input devices attached to a computing device. The extensible input stack comprises a plurality of stack layers. Each of the plurality of stack layers performs a particular set of processing with respect to the input device data, among other operations. Each of the plurality of stack layers comprises a code interface, which is used to provide and/or or receive data from the input device and/or other stack layers. Each of the stack layers is extensible to include additional functionality to support new input devices. By separating out the functionality performed by the input stack into separate stack layers, and having each layer accessible via a code interface, the functionality of each of stack layers may be easily extended to support any type of input device.

公开(公告)号：WO2015031115A1

公开(公告)日：2015-03-05

申请号：PCT/US2014/051758

申请日：2014-08-19

Applicant: QUALCOMM INCORPORATED

Inventor： SENGOKU, Shoichiro ,  WIETFELDT, Richard Dominic ,  WILEY, George Alan

IPC: G06F13/26

CPC classification number: G06F13/4226 ,  G06F13/22 ,  G06F13/24 ,  G06F13/26 ,  G06F2211/001 ,  G06F2211/002

Abstract: A master device is provided which is coupled to a shared single line interrupt request (IRQ) bus and a control data bus. The master device group slave devices coupled to the shared single line IRQ bus into one or more groups, where each group is associated with a different IRQ signal. The master device then monitors the IRQ bus to ascertain when an IRQ signal is asserted by at least one slave device. The master device then identifies a group to with which the IRQ signal is associated. The slave devices for the identified group are then scanned or queried by the master device to ascertain which slave device asserted the IRQ signal on the IRQ bus. Each group uses a distinguishable IRQ signal to allow the master device to ascertain which group to query or scan.

Abstract translation: 提供了一个主器件，其耦合到共享单线中断请求（IRQ）总线和控制数据总线。 主设备组从设备将共享单线IRQ总线耦合到一个或多个组中，其中每个组与不同的IRQ信号相关联。 然后，主设备监视IRQ总线以确定至少一个从设备何时确定IRQ信号。 然后，主设备识别与IRQ信号相关联的组。 然后，由主设备扫描或查询所识别的组的从设备，以确定哪个从设备在IRQ总线上断言IRQ信号。 每个组使用可区分的IRQ信号来允许主设备确定哪个组进行查询或扫描。

公开(公告)号：WO2007120804A2

公开(公告)日：2007-10-25

申请号：PCT/US2007009087

申请日：2007-04-12

Applicant: INTEL CORP ,  HARRIMAN DAVID

Inventor： HARRIMAN DAVID

CPC classification number: G06F13/4226

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for multiplexing a parallel bus interface with a flash memory interface. In some embodiments, an integrated circuit includes a parallel bus interface to communicate parallel bus interface signals. The integrated circuit may also include logic to multiplex flash memory device interface signals and parallel bus interface signals on the parallel bus interface.

Abstract translation: 本发明的实施例通常涉及用于将并行总线接口与闪存接口多路复用的系统，方法和装置。 在一些实施例中，集成电路包括并行总线接口以传送并行总线接口信号。 集成电路还可以包括在并行总线接口上复用闪存设备接口信号和并行总线接口信号的逻辑。

公开(公告)号：WO0175618A3

公开(公告)日：2002-03-28

申请号：PCT/US0109907

申请日：2001-03-28

Applicant: DATAPLAY INC

Inventor： GURKOWSKI MARK J ,  KEELER STAN M ,  LEE LANE W

IPC: G06F13/42 ,  G06F13/38

CPC classification number: G06F13/4226

Abstract: An interface protocol for transmitting variable-sized packets between a host system and a storage device. The protocol supports a plurality of signals for transmitting data between the host system and the storage device. One or more address signals indicate whether the packet includes command, data, or status information. An enable signal indicates when the packets may be transmitted to and from the storage device. Read and write strobe signals are also included to allow the host to request data from and transmit data to the storage device. The protocol includes an extensible command set which includes a function code, one or more interrupt requests, and signals to indicate when the storage device is busy, when the storage device is ready to transfer data, when the storage device is ready to receive bytes from a command packet, when the storage device is ready to receive or transmit a data block, and when the storage device is ready to transmit status bytes.

Abstract translation: 一种用于在主机系统和存储设备之间传输可变大小的分组的接口协议。 该协议支持用于在主机系统和存储设备之间传输数据的多个信号。 一个或多个地址信号指示分组是否包括命令，数据或状态信息。 启用信号指示何时可以将数据包传输到存储设备和从存储设备发送。 还包括读取和写入选通信号，以允许主机向存储设备请求数据和传输数据。 该协议包括可扩展命令集，其包括功能码，一个或多个中断请求，以及当存储设备准备好传输数据时，当存储设备正在忙时指示的信号，当存储设备准备好接收字节时 当存储设备准备好接收或发送数据块时，以及当存储设备准备好发送状态字节时的命令分组。

公开(公告)号：WO99015981A1

公开(公告)日：1999-04-01

申请号：PCT/US1998/014682

申请日：1998-07-15

IPC: G06F13/40 ,  G06F13/42 ,  H04L7/04

CPC classification number: G06F13/4226 ,  G06F13/4045 ,  H04L7/04

Abstract: A synchronous bus system that enables the bus lengths between devices to be extended such that the timing budget is more than one clock cycle. A reset process (215 and 220) resets the transmission and reception circuitry and both circuitry function according to prespecified parameters relative to the deassertion of the reset signal such that the amount of logic required to latch and sample the data is minimized. As the timing budget is not limited to one clock cycle, devices can be spaced further apart providing more physical space for devices. Furthermore, skew sensitivity is reduced as the skew is distributed over multiple clock periods.

Abstract translation: 同步总线系统能够延长设备之间的总线长度，使得定时预算超过一个时钟周期。 复位处理（215和220）复位发送和接收电路，并且两个电路根据预先指定的参数相对于重置信号的去激活而起作用，使得锁存和采样数据所需的逻辑量最小化。 由于定时预算不限于一个时钟周期，所以设备可以进一步分开，为设备提供更多的物理空间。 此外，由于歪斜分布在多个时钟周期内，偏斜灵敏度会降低。

公开(公告)号：WO1993008029A1

公开(公告)日：1993-04-29

申请号：PCT/JP1992000337

申请日：1992-03-19

Applicant: SEIKO EPSON CORPORATION

Inventor： SEIKO EPSON CORPORATION ,  WAKABAYASHI, Ken-ichi ,  TAKAYAMA, Chitoshi ,  SHIOZAKI, Tadashi

IPC: B41J29/00

CPC classification number: G06K15/128 ,  B41J5/44 ,  B41J29/00 ,  G06F13/385 ,  G06F13/4226 ,  G06K15/00 ,  G06K2215/0002 ,  G06K2215/0025 ,  G06K2215/0082

Abstract: In case of processing information by mounting an additional control device on an electronic equipment, data are transferred at a high efficiency between the electronic equipment and the additional control device. The electronic equipment to which data are transferred, e.g., an electronic control equipment in a printer outputs the data to be transferred by reflecting the lower order eight bits of an address signal line (CAB). By this assignment of an address, the data corresponding to the address is read out from a ROM (671), and is latched by latches (651, 652), and further, the additional control device is informed of the latching of the data by an interruption request signal AMDINTO or a signal EWRDY. When a microprocessor of the additional control device, i.e., a cartridge reads the data latched in the latches (651, 652) via a data bus (DB29), the data transfer from the electronic equipment is completed.

Abstract translation: 在通过在电子设备上安装附加控制装置来处理信息的情况下，在电子设备和附加控制装置之间高效地传送数据。 传送数据的电子设备，例如打印机中的电子控制设备，通过反映地址信号线（CAB）的低位8位来输出要传送的数据。 通过该地址的分配，从ROM（671）中读出对应于该地址的数据，并由锁存器（651,652）锁存，此外，附加控制装置被通知数据的锁存 中断请求信号AMDINTO或信号EWRDY。 当附加控制装置的微处理器（即，盒式盒）经由数据总线（DB29）读取锁存器（651,652）中锁存的数据时，完成了来自电子设备的数据传送。

公开(公告)号：WO2016048329A1

公开(公告)日：2016-03-31

申请号：PCT/US2014/057487

申请日：2014-09-25

Applicant: MICRO MOTION, INC.

Inventor： HAYS, Paul J. ,  EYRE, Chris E.

IPC: G06F13/42

CPC classification number: G06F13/4226 ,  G06F13/4213 ,  G06F13/4239 ,  G06F13/4282 ,  H04W56/00

Abstract: A method for stack timing adjustment for serial communications is provided. The method includes receiving a USB communication, decoding the USB communication into UART frames, and adjusting the timing of the UART frames according to a serial protocol.

Abstract translation: 提供了一种用于串行通信的堆栈定时调整的方法。 该方法包括接收USB通信，将USB通信解码为UART帧，以及根据串行协议调整UART帧的定时。

公开(公告)号：WO2015187246A1

公开(公告)日：2015-12-10

申请号：PCT/US2015/024653

申请日：2015-04-07

Applicant: APPLE INC.

Inventor： SMITH, Michael, J. ,  DE CESARE, Josh, P. ,  TRIPATHI, Brijesh ,  IWAMOTO, Derek ,  KEIL, Shane, J.

IPC: G06F13/38

CPC classification number: G06F13/4226 ,  G06F13/105 ,  G06F13/28 ,  G06F13/385 ,  G06F13/4022 ,  G06F13/4059

Abstract: An interface emulator for an IC is disclosed. An interface emulator includes a first first-in, first-out memory (FIFO) and a second FIFO. The first FIFO is coupled to receive data from an access port and a second FIFO coupled to receive data from at least one functional unit in the IC. The access port may be coupled to a device that is external to the IC. The external device may write information into the first FIFO, and this information may subsequently be read by a functional unit in the IC. Similarly, the functional unit may write information into the second FIFO, with the external device subsequently reading the information. Information may be written into the FIFOs in accordance with a predefined protocol. Thus, a particular type of interface may be emulated even though the physical connection and supporting circuitry for that interface is not otherwise implemented in the IC.

Abstract translation: 公开了一种用于IC的接口仿真器。 接口仿真器包括第一先入先出存储器（FIFO）和第二FIFO。 第一FIFO被耦合以从接入端口接收数据，并且第二FIFO被耦合以从IC中的至少一个功能单元接收数据。 访问端口可以耦合到IC外部的设备。 外部设备可以将信息写入第一FIFO，并且该信息随后可以由IC中的功能单元读取。 类似地，功能单元可以将信息写入第二FIFO，随后外部设备读取信息。 可以根据预定义的协议将信息写入FIFO。 因此，即使在IC中没有实现用于该接口的物理连接和支持电路，也可以模拟特定类型的接口。

公开(公告)号：WO2014150529A1

公开(公告)日：2014-09-25

申请号：PCT/US2014/023508

申请日：2014-03-11

Applicant: QUALCOMM INCORPORATED

Inventor： HOLLIS, Timothy Mowry

IPC: G06F13/42

CPC classification number: G06F13/4286 ,  G06F13/287 ,  G06F13/4221 ,  G06F13/4226 ,  H04L7/04 ,  Y02D10/14 ,  Y02D10/151

Abstract: A method for data transmission is described. A signaling speed of operation of an electronic device is determined. A data bus inversion algorithm is selected based on the signaling speed of operation. The selected data bus inversion algorithm is used to encode data. The encoded data and a data bus inversion flag are sent to a receiver over a transmission medium.

Abstract translation: 描述用于数据传输的方法。 确定电子设备的信号传输速度。 基于信令操作速度选择数据总线反演算法。 所选择的数据总线反演算法用于对数据进行编码。 编码数据和数据总线反转标志通过传输介质发送到接收器。

公开(公告)号：WO9750040A3

公开(公告)日：2002-12-12

申请号：PCT/DE9701219

申请日：1997-06-16

Applicant: SIEMENS AG ,  OBERLAENDER KLAUS ,  PFAB STEFAN

Inventor： OBERLAENDER KLAUS ,  PFAB STEFAN

IPC: G06F13/42 ,  G06F15/78 ,  H01R4/24 ,  H01R13/512 ,  H01R13/56 ,  H01R13/658

CPC classification number: G06F13/4226 ,  G06F15/7842 ,  H01R4/2433 ,  H01R13/512 ,  H01R13/565 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

Abstract: A microprocessor device has an arithmetic unit (CPU) which converts the commands stored in a program storage for controlling the various elements of the microprocessor into arithmetic and/or logic operations, and a data and/or control bus (10, 11) for transmitting data and for accessing CPU-internal and/or peripheral-bound special function registers (18) associated to the arithmetic unit. A coherent memory block (24) with memory cells (31a to 31h) of the random access type (RAM is associated by the data and/or control bus (10, 11) to the arithmetic unit. The memory block (24) has its own address decoding and bus driving circuit, a first storage area which can be used or accessed at will and a second directly addressable storage area bound to the peripheral units. A release device (26) associated to the memory block locks or releases the transmission of data from the second storage area to the data and/or control bus (10, 11).

Abstract translation: 本发明涉及一种具有算术逻辑单元（CPU），其中存储在程序存储器命令中的数据，用于控制的算术和/或逻辑运算的形式，微处理器的各种组件中实现，数据和/或控制总线的微处理器装置（10 ，11）（用于数据传输以及用于访问CPU内部和/或外周结合的特殊功能寄存器18），其被分配给该算术单元。 所述计算单元是由所述数据和/或控制线（10，11）是被分配的存储器（24），其具有存储器的随机存取类型（RAM）的小区（31a至31H）的连续块，它有自己的地址解码器和总线驱动器电路的装置，和第一 可用根据需要或具有可访问的存储器区域和第二，外周未结合的和直接寻址存储器区域，其中，所述存储器块包括释放装置（26）与数据内容上的数据和/或控制线（10，11，其输出从所述第二存储区域相关联的 ）锁或释放。