公开(公告)号：WO2022134162A1

公开(公告)日：2022-06-30

申请号：PCT/CN2020/141291

申请日：2020-12-30

Applicant: 光华临港工程应用技术研发（上海）有限公司

Inventor： 刘盼 ,  李健 ,  唐久阳 ,  张靖 ,  樊嘉杰 ,  张国旗

IPC: H01L21/28 ,  H01L21/48 ,  H01L23/48 ,  H01L29/40

Abstract: 本发明提供了一种可转移的柔性互联结构的制备方法，包括如下步骤：提供一转移衬底，所述转移衬底表面具有均苯型聚酰亚胺薄膜层、连续的金属导电层、图形化的聚酰亚胺薄膜层；提供一器件衬底，所述器件衬底表面具有图形化金属电极；以所述图形化金属电极和所述图形化聚酰亚胺薄膜层为中间层，将所述器件衬底与所述支撑衬底键合；去除转移衬底和部分的均苯型聚酰亚胺薄膜层，至暴露出所述连续的金属导电层。

公开(公告)号：WO2022123026A1

公开(公告)日：2022-06-16

申请号：PCT/EP2021/085225

申请日：2021-12-10

Applicant: MQSEMI AG [CH]/[CH]

Inventor： RAHIMO, Manuf

IPC: H01L29/739 ,  H01L29/10 ,  H01L29/417 ,  H01L29/06 ,  H01L29/08 ,  H01L29/40

Abstract: A Metal Oxide Semiconductor (MOS) transistor cell design has a source region and a first base layer extending in a third dimension. When a control voltage greater than a threshold value is applied on the gate trench, electrons flow from a singular point within the source region, into a radial MOS channel formed on the lateral walls of those trench regions surrounded by the first base layer, but not abutting on the higher doped second base layer. The MOS channel width is determined by a quadrant centred on the singular point and with a radius equal to the separation region between the singular point and the maximum surface doping concentration point in the first base layer.

公开(公告)号：WO2022098627A1

公开(公告)日：2022-05-12

申请号：PCT/US2021/057675

申请日：2021-11-02

Applicant: WOLFSPEED, INC.

Inventor： VAN BRUNT, Edward Robert ,  MCPHERSON, Joe W. ,  HARRINGTON, III, Thomas E. ,  RYU, Sei-Hyung ,  HULL, Brett ,  JI, In-Hwan

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/40

Abstract: Semiconductor devices, and more particularly passivation structures for semiconductor devices are disclosed. A semiconductor device may include an active region, an edge termination region that is arranged along a perimeter of the active region, and a passivation structure that may form a die seal along the edge termination region. The passivation structure may include a number of passivation layers in an arrangement that improves mechanical strength and adhesion of the passivation structure along the edge termination region. An interface formed by at least one of the passivation layers may be provided with a pattern that serves to more evenly distribute forces related to thermal expansion and contraction during power cycling, thereby reducing cracking and delamination in the passivation structure. A patterned layer may be at least partially embedded in the passivation structure in an arrangement that forms the corresponding pattern in overlying portions of the passivation structure.

公开(公告)号：WO2022095347A1

公开(公告)日：2022-05-12

申请号：PCT/CN2021/089923

申请日：2021-04-26

Applicant: 中国电子科技集团公司第二十四研究所

Inventor： 谭开洲 ,  肖添 ,  张嘉浩 ,  杨永晖 ,  李孝权 ,  王鹏飞 ,  裴颖 ,  李光波 ,  蒋和全 ,  张培健 ,  邱盛 ,  陈良 ,  崔伟

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/40 ,  H01L21/336

Abstract: 本发明提供了一种电阻场板电导调制场效应MOS器件及其制备方法，本发明提供的电阻场板电导调制场效应MOS器件，在槽栅MOS器件的基础上，于漂移区中增设一个同时与槽栅结构和漏极结构电连接的半绝缘电阻场板，在槽栅结构控制MOS沟道的通断的同时，通过半绝缘电阻场板调节漂移区中的杂质浓度，进而调制导通态漂移区电导和截止态高压阻断电场分布，可以获得更低的导通电阻特性；同时，本发明提供的电阻场板电导调制场效应MOS器件制备方法，在工艺上采用了基于深槽刻蚀的现代2.5维立体加工工艺，利于结构小型化设计和高密度化设计，更适应现代集成半导体器件More than Moore(超越摩尔)的发展方向。

公开(公告)号：WO2022060837A1

公开(公告)日：2022-03-24

申请号：PCT/US2021/050455

申请日：2021-09-15

Applicant: MURATA MANUFACTURING CO., LTD. ,  YOSHIDA, Koji

Inventor： YOSHIDA, Koji

IPC: H01L21/768 ,  A61B5/00 ,  A61B5/0408 ,  H01L23/48 ,  H01L29/40

Abstract: A conductive electrode that includes a substrate having first and second opposed main surfaces and a plurality of trenches extending between the first and second opposed main surfaces; and a conductive material within the plurality of trenches and extending between the first and second opposed main surfaces so as to provide an electrically conductive path between the first and second opposed main surfaces.

公开(公告)号：WO2022011835A1

公开(公告)日：2022-01-20

申请号：PCT/CN2020/117288

申请日：2020-09-24

Applicant: 苏州东微半导体有限公司

Inventor： 刘磊 ,  毛振东 ,  徐真逸 ,  龚轶

IPC: H01L29/06 ,  H01L29/78 ,  H01L21/04 ,  H01L21/336 ,  H01L21/265 ,  H01L29/40 ,  H01L29/66477

Abstract: 本申请属于半导体功率器件技术领域，公开了一种半导体功率器件及其制造方法，半导体功率器件包括：n型外延层；凹陷在所述n型外延层内的若干个元胞区沟槽和若干个终端区沟槽，所述终端区沟槽的深度小于所述元胞区沟槽的深度；位于所述n型外延层内且位于所述终端区沟槽下方的p型掺杂区，每个所述终端区沟槽的下方均设置有所述p型掺杂区。

公开(公告)号：WO2022006731A1

公开(公告)日：2022-01-13

申请号：PCT/CN2020/100611

申请日：2020-07-07

Applicant: INNOSCIENCE (ZHUHAI) TECHNOLOGY CO., LTD.

Inventor： WANG, Chao ,  CHANG, Ming-Hong

IPC: H01L29/778 ,  H01L29/40

Abstract: A semiconductor device and a fabrication method thereof are disclosed. The semiconductor device includes a first nitride semiconductor layer (111), a second nitride semiconductor layer (113), a gate structure (120), and a field plate (130). The first nitride semiconductor layer (111) has a first surface. The second nitride semiconductor layer (113) is formed on the first surface of the first nitride semiconductor layer (111) and has a greater bandgap than that of the first nitride semiconductor layer (111). The gate structure (120) is disposed on the second nitride semiconductor layer (113). The field plate (130) includes a first portion (133) and a second portion (131) connected to the first portion (133). The first portion (133) has a first surface (133b) substantially in parallel to the first surface of the first nitride semiconductor layer (111) along a first direction, and a second surface (133c) adjacent to the first surface of the first portion (133). The first surface (133b) of the first portion (133) of the field plate (130) and the second surface (133c) of the first portion (133) of the field plate (130) define a first angle of about 90°.

公开(公告)号：WO2021254617A1

公开(公告)日：2021-12-23

申请号：PCT/EP2020/066907

申请日：2020-06-18

Applicant: DYNEX SEMICONDUCTOR LIMITED ,  ZHUZHOU CRRC TIMES SEMICONDUCTOR CO. LTD

Inventor： NGWENDSON, Luther-King ,  DEVINY, Ian

IPC: H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/739 ,  H01L29/66 ,  H01L29/0696 ,  H01L29/401 ,  H01L29/407 ,  H01L29/417 ,  H01L29/42368 ,  H01L29/66348 ,  H01L29/7397

Abstract: We describe herein a gate controlled bipolar semiconductor device comprising a collector region (104) of a first conductivity type, a drift region (106, 108) of a second conductivity type located over the collector region, a body region of a first conductivity type (110) located over the drift region, a body region of a second conductivity type (112) located over the drift region, at least one first contact region of a second conductivity type located above the body region and having a higher doping concentration compared to the body region, at least one second contact region of a first conductivity type (116) located laterally adjacent to the at least one first contact region, the at least one second contact region having a higher doping concentration than the body region, at least one active trench (124) extending from a surface into the drift region, wherein the at least one first contact region adjoins at least one active trench so that, in use, a channel region is formed along said at least one active trench and within the body region, and at least two auxiliary trenches (118) extending from the surface into the drift region. The at least two auxiliary trenches each comprise an insulation layer (122) along the vertical sidewalls and the bottom surface. The thickness of the insulation layer along the two vertical sidewalls of the at least two auxiliary trenches is less than 1500A. The body region of a first conductivity type and the body region of a second conductivity type are both located at least between two adjacent auxiliary trenches. Possibly the device furthermore comprises an emitter trench (336) between two active trenches (124) and being recessed from the top surface.

公开(公告)号：WO2021232813A1

公开(公告)日：2021-11-25

申请号：PCT/CN2020/140672

申请日：2020-12-29

Applicant: 华润微电子（重庆）有限公司

Inventor： 方冬 ,  肖魁

IPC: H01L29/40 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L21/336 ,  H01L21/28

Abstract: 一种沟槽栅金属氧化物半导体场效应管及其制备方法，所述沟槽栅金属氧化物半导体场效应管包括：第一导电类型漂移区(100)；第二导电类型体区(110)，形成于漂移区(100)内；第一导电类型源区(111)，形成于体区(110)内，源区(111)开设有延伸至漂移区(100)内的沟槽；沟槽内填充有相互隔离的第一导电结构(130)和第二导电结构(140)，第一导电结构(130)底部深度大于第二导电结构(140)底部深度，定义第一导电结构(130)中深度超过第二导电结构(140)底部深度的部分为场板调节结构；第一掺杂区(160)，具有第二导电类型，形成于漂移区(100)内且与体区(110)相接，第一掺杂区(160)的底部深度超过场板调节结构的顶部深度；源区(111)、体区(110)与源极连接；第二导电结构(140)与栅极连接。

公开(公告)号：WO2021084070A1

公开(公告)日：2021-05-06

申请号：PCT/EP2020/080513

申请日：2020-10-30

Applicant: INFINEON TECHNOLOGIES AUSTRIA AG

Inventor： MAHMOUD, Ahmed ,  POPESCU, Dan Horia ,  ROCHEL, Markus

IPC: H01L29/423 ,  H01L29/739 ,  H01L29/78 ,  H01L29/06 ,  H01L29/40 ,  H01L29/417

Abstract: A semiconductor device, comprises a semiconductor body (100) comprising a first surface (101), a second surface (102) opposite to the first surface (101) in a vertical direction (y), an edge termination region (210), and an active region (220) arranged adjacent to the edge termination region (210) in a horizontal direction. The semiconductor device further comprises a plurality of transistor cells (30) at least partly integrated in the active region (220), each transistor cell (30) comprising a source region (31), a body region (32), and a drift region (35) separated from the source region (31) by the body region (32). The semiconductor device further comprises a gate electrode (33) arranged in the active region (220) and dielectrically insulated from the body regions (32) of the plurality of transistor cells (30), a circumferential electrically conducting layer (60) arranged above the first surface (101) and in the edge termination region (210), and a gate pad (46) electrically coupled to the electrically conductive layer (60). The gate pad (46) partially covers the electrically conducting layer (60), the electrically conducting layer (60) extends around and electrically contacts the gate electrode (33), and a contact between the electrically conductive layer (60) and the gate electrode (33) is completely interrupted along the section of the electrically conductive layer (60) that is covered by the gate pad (46).