公开(公告)号：WO2014126555A1

公开(公告)日：2014-08-21

申请号：PCT/US2013/025896

申请日：2013-02-13

Applicant: VIOLIN MEMORY, INC.

Inventor： DE LA IGLESIA, Erik ,  SIKDAR, Som ,  PARKER, David ,  DOMMETI, Sivaram

IPC: G06F12/00 ,  G06F12/08

CPC classification number: G06F12/0871

Abstract: A hardware search structure determines the status of cache lines associated with a large disk array and at the same time reduces the amount of memory space needed for tracking the status. The search structure is configurable in hardware to different cache line sizes and different primary and secondary index sizes. A maintenance feature invalidates state record entries based both on their time stamps and on associated usage statistics.

Abstract translation: 硬件搜索结构确定与大磁盘阵列相关联的高速缓存行的状态，同时减少跟踪状态所需的存储器空间量。 搜索结构可以在硬件中配置为不同的高速缓存行大小和不同的主索引和辅助索引大小。 维护功能使状态记录条目基于其时间戳和关联的使用统计信息无效。

公开(公告)号：WO2014078481A1

公开(公告)日：2014-05-22

申请号：PCT/US2013/070003

申请日：2013-11-14

Applicant: VIOLIN MEMORY INC.

Inventor： FORTIN, Kyle

IPC: G06F12/02 ,  G06F13/14 ,  G06F9/06

CPC classification number: G06F9/526 ,  G06F12/0837 ,  G06F2209/523

Abstract: A system and method of managing the storage of data is described where a plurality of requesting entities can be permitted access to a shared data resource. When a modification to the data is needed, the request may be executed as an atomic operation. To do this the memory region is temporarily locked until the atomic operation is completed so that other operations related to the data are deferred until the atomic operation has completed. The lock is secured by reference to a data array or register of fixed length where the address of the locked data region is represented by a bit, the position of which is determined by computing a hash value of the address modulo the length of the lock register.

Abstract translation: 描述了管理数据存储的系统和方法，其中允许多个请求实体访问共享数据资源。 当需要对数据进行修改时，请求可以作为原子操作执行。 为此，内存区域暂时被锁定，直到原子操作完成，以便与数据相关的其他操作被延迟到原子操作完成。 锁定通过参考固定长度的数据阵列或寄存器来保护，其中锁定的数据区域的地址由位表示，其位置通过计算锁定寄存器的长度的地址的散列值来确定 。

公开(公告)号：WO2014047159A1

公开(公告)日：2014-03-27

申请号：PCT/US2013/060375

申请日：2013-09-18

Applicant: VIOLIN MEMORY INC.

Inventor： PIGNATELLI, David, J.

IPC: G06F12/08 ,  G06F13/00

CPC classification number: G06F12/0246 ,  G06F3/0611 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0688 ,  G06F11/108 ,  G06F2211/1009 ,  G06F2212/7203

Abstract: A method of managing a non-volatile memory system is described where data elements stored in a buffer are characterized by attributes and a write data tag is created for the data elements. A plurality of write data tag queues is maintained so that different data attributes may be applied as sorting criteria when the data elements are formed into pages for storage in the non-volatile memory. The memory system may be organized as a RAID system and a write data tag queue may be associated with a specific RAID group such that the data pages may be written from a buffer to the non-volatile memory in accordance with the results of sorting each write data queue. The data elements stored in the buffer may be received from a user, or be read from the non-volatile memory during the performance of system overhead operations.

Abstract translation: 描述了管理非易失性存储器系统的方法，其中存储在缓冲器中的数据元素由属性表征，并且为数据元素创建写入数据标签。 维持多个写数据标签队列，使得当数据元素形成为用于存储在非易失性存储器中的页面时，可以将不同的数据属性应用为排序标准。 存储器系统可以被组织为RAID系统，并且写数据标签队列可以与特定RAID组相关联，使得可以根据排序每个写入的结果将数据页从缓冲器写入非易失性存储器 数据队列。 存储在缓冲器中的数据元素可以从用户接收，或者在执行系统开销操作期间从非易失性存储器读取。

公开(公告)号：WO2014004972A1

公开(公告)日：2014-01-03

申请号：PCT/US2013/048476

申请日：2013-06-28

Applicant: VIOLIN MEMORY INC.

Inventor： SISLER, John, Robert

IPC: G06F1/26 ,  G06F1/16

CPC classification number: G06F1/183 ,  G06F1/181 ,  G06F1/188 ,  G06F1/20 ,  H05K7/1492

Abstract: A power supply and circuit module includes a housing, a power supply and a circuit module received in the housing. The power supply and the circuit module can be removably installed into and removed from a cage of an electronic system as a unit by a sliding action. The cage includes a first bottom plate, a backplane connected to the first bottom plate. A plurality of standoffs are formed on the first bottom plate for supporting a motherboard thereon. An electrical connector, such as a card connector, is directly formed on the backplane for connecting a circuit card.

Abstract translation: 电源和电路模块包括壳体，电源和容纳在壳体中的电路模块。 电源和电路模块可以通过滑动动作可移除地安装到作为一个单元的电子系统的笼中。 保持架包括第一底板，连接到第一底板的背板。 在第一底板上形成多个支座，用于在其上支撑母板。 诸如卡连接器的电连接器直接形成在背板上用于连接电路卡。

公开(公告)号：WO2013184923A1

公开(公告)日：2013-12-12

申请号：PCT/US2013/044527

申请日：2013-06-06

Applicant: VIOLIN MEMORY, INC.

Inventor： BENNETT, Jon, C. R. ,  BIEDERMAN, Daniel, C. ,  SMITH, David, M.

IPC: G11C7/10

CPC classification number: G06F11/1092

Abstract: A memory system and a method for managing the system is described. The system is configured such a plurality of system controllers, which may be RAID controllers, receive requests from the external environment and distribute the requests to a plurality of memory modules such that data may be stored in the memory modules. A global sequence number is assigned to the data of a data stripe so that the operations related to the data stripe are performed in an ordered manner so that the data remains consistent. A plurality of system controllers may comprise a domain and access a plurality of memory controllers and a plurality of domains may include at least one common memory module. A plurality of groups of controllers may communicate with a switch or with a representative controller so as to coordinate the assignment of global sequence numbers.

Abstract translation: 描述了用于管理系统的存储器系统和方法。 该系统被配置为这样的多个系统控制器，其可以是RAID控制器，从外部环境接收请求并将请求分发到多个存储器模块，使得可以将数据存储在存储器模块中。 将全局序列号分配给数据条带的数据，使得与数据条带相关的操作以有序的方式执行，使得数据保持一致。 多个系统控制器可以包括域并访问多个存储器控制器，并且多个域可以包括至少一个公共存储器模块。 多组控制器可以与开关或代表控制器进行通信，以协调全局序列号的分配。

公开(公告)号：WO2013012673A3

公开(公告)日：2013-03-21

申请号：PCT/US2012046448

申请日：2012-07-12

Applicant: VIOLIN MEMORY INC ,  STEPHENS DONPAUL C

Inventor： STEPHENS DONPAUL C

IPC: G06F12/02 ,  G11C16/06

CPC classification number: G06F3/0638 ,  G06F3/0607 ,  G06F3/061 ,  G06F3/0688 ,  G06F11/108

Abstract: A data storage array is described, having a plurality of solid state disks configured as a RAID group. User data is mapped and managed on a page size scale by the controller, and the data is mapped on a block size scale by the solid state disk. The writing of data to the solid state disks of the RAID group is such that reading of data sufficient to reconstruct a RAID stripe is not inhibited by the erase operation of a disk to which data is being written.

Abstract translation: 描述了具有被配置为RAID组的多个固态盘的数据存储阵列。 用户数据由控制器以页面大小的尺寸进行映射和管理，并且数据通过固态盘以块大小的尺寸映射。 将数据写入RAID组的固态磁盘使得读取足以重建RAID条带的数据不被写入数据的盘的擦除操作所禁止。

公开(公告)号：WO2013012673A2

公开(公告)日：2013-01-24

申请号：PCT/US2012/046448

申请日：2012-07-12

Applicant: VIOLIN MEMORY, INC. ,  STEPHENS, Donpaul, C.

Inventor： STEPHENS, Donpaul, C.

IPC: G06F12/02 ,  G11C16/06

CPC classification number: G06F3/0638 ,  G06F3/0607 ,  G06F3/061 ,  G06F3/0688 ,  G06F11/108

Abstract: A data storage array is described, having a plurality of solid state disks configured as a RAID group. User data is mapped and managed on a page size scale by the controller, and the data is mapped on a block size scale by the solid state disk. The writing of data to the solid state disks of the RAID group is such that reading of data sufficient to reconstruct a RAID stripe is not inhibited by the erase operation of a disk to which data is being written.

Abstract translation: 描述了一种数据存储阵列，其具有配置为RAID组的多个固态硬盘。 用户数据由控制器以页面大小的比例进行映射和管理，并且数据通过固态硬盘映射到块大小比例。 将数据写入RAID组的固态磁盘使得读取足以重建RAID条带的数据不会被正被写入数据的磁盘的擦除操作所抑制。

公开(公告)号：WO2013009994A2

公开(公告)日：2013-01-17

申请号：PCT/US2012/046487

申请日：2012-07-12

Applicant: VIOLIN MEMORY, INC. ,  BENNETT, Jon, C., R. ,  SMITH, David, M. ,  BIEDERMAN, Daniel, C.

Inventor： BENNETT, Jon, C., R. ,  SMITH, David, M. ,  BIEDERMAN, Daniel, C.

IPC: G06F13/14 ,  G06F13/16

CPC classification number: G06F3/0688 ,  G06F3/0611 ,  G06F3/0614 ,  G06F3/0659 ,  G06F3/0689

Abstract: A memory system and a method for managing the system is described. The system is configured such a plurality of system controllers, which may be RAID controllers, receive requests from the external environment and distribute the requests to a plurality of memory modules such that data may be stored in the memory modules. A global sequence number is assigned to the data of a data stripe so that the operations related to the data stripe are performed in an ordered manner so that the data remains consistent. A plurality of system controllers may comprise a domain and access a plurality of memory controllers and a plurality of domains may include at least one common memory module.

Abstract translation: 描述了用于管理系统的存储器系统和方法。 该系统被配置为这样的多个系统控制器，其可以是RAID控制器，从外部环境接收请求并将请求分发到多个存储器模块，使得可以将数据存储在存储器模块中。 将全局序列号分配给数据条带的数据，使得与数据条带相关的操作以有序的方式执行，使得数据保持一致。 多个系统控制器可以包括域并访问多个存储器控制器，并且多个域可以包括至少一个公共存储器模块。

公开(公告)号：WO2011081957A2

公开(公告)日：2011-07-07

申请号：PCT/US2010/060408

申请日：2010-12-15

Applicant: VIOLIN MEMORY, INC. ,  TALAGALA, Nisha ,  KERCHEVAL, Berry ,  PATTERSON, Martin ,  PERNICKA, Edward ,  BOWEN, James

Inventor： TALAGALA, Nisha ,  KERCHEVAL, Berry ,  PATTERSON, Martin ,  PERNICKA, Edward ,  BOWEN, James

IPC: G06F12/08 ,  G06F9/06

CPC classification number: G06F12/0246 ,  G06F12/02 ,  G06F12/0806 ,  G06F12/0866 ,  G06F12/0897 ,  G06F2212/225 ,  G06F2212/7211

Abstract: A multi-tiered cache manager and methods for managing multi-tiered cache are described. Multi-tiered cache manager causes cached data to be initially stored in the RAM elements and selects portions of the cached data stored in the RAM elements to be moved to the flash elements. Each flash element is organized as a plurality of write blocks having a block size and wherein a predefined maximum number of writes is permitted to each write block. The portions of the cached data may be selected based on a maximum write rate calculated from the maximum number of writes allowed for the flash device and a specified lifetime of the cache system.

Abstract translation: 描述了用于管理多层高速缓存的多层高速缓存管理器和方法。 多层高速缓存管理器使高速缓存的数据最初存储在RAM元件中，并选择存储在RAM元件中的部分高速缓存数据移动到闪存元件。 每个闪存元件被组织为具有块大小的多个写入块，并且其中每个写入块允许预定义的最大写入次数。 高速缓存数据的部分可以基于从允许用于闪存设备的最大写入次数和高速缓存系统的指定生存期计算的最大写入速率来选择。

公开(公告)号：WO2011044515A2

公开(公告)日：2011-04-14

申请号：PCT/US2010052074

申请日：2010-10-08

Applicant: VIOLIN MEMORY INC ,  BENNETT JON C R

Inventor： BENNETT JON C R

IPC: G06F12/16 ,  G06F13/14

CPC classification number: G06F11/1092 ,  G06F2211/1061

Abstract: A data memory system is described, where there may be an asymmetry in the time needed to write or erase data and the time needed to read data. The data may be stored using a RAID data storage arrangement and the reading, writing and erasing operations on the modules arranged such that the erasing and writing operations may be performed without significant latency for performing a read operation. Where a failure of a memory module in the memory system occurs, methods for recovering the data of the failed module are disclosed which may selected in accordance with policies that may relate to the minimizing the possibility of irretrievable data loss, or degradation of latency performance.

Abstract translation: 描述了一种数据存储系统，其中写入或擦除数据所需的时间可能不对称，以及读取数据所需的时间。 可以使用RAID数据存储装置存储数据，并且对布置的模块进行读取，写入和擦除操作，使得可以执行擦除和写入操作而没有用于执行读取操作的显着延迟。 在存储器系统中的存储器模块发生故障的情况下，公开了用于恢复故障模块的数据的方法，其可以根据可能涉及最小化不可恢复的数据丢失的可能性或延迟性能下降的策略来选择。