公开(公告)号：WO2009046300A3

公开(公告)日：2009-05-22

申请号：PCT/US2008078752

申请日：2008-10-03

Applicant: VIOLIN MEMORY INC ,  JONES JAMES H ,  DRUCKER KEVIN D ,  BENNETT JON C R

Inventor： JONES JAMES H ,  DRUCKER KEVIN D ,  BENNETT JON C R

IPC: G06F13/16

CPC classification number: G06F13/4243 ,  Y02D10/14 ,  Y02D10/151

Abstract: A memory system is described, where the transmission time of data between memory modules is managed so that the overall time delay between specified points in the memory system is maintained a constant. Each lane of a multilane bus may be separately managed, and a data frame evaluated at the destination module, without a need for deskewing at intermediate modules. The time delay in propagation of the data through a module, which may have a switch to route the data, is reduced by operating the data path through the module at one or more submultiples of the bus serial data rate, and selecting the sampling point of the received data so that variations in time delay due to temperature changes or ageing are accommodated.

Abstract translation: 描述了一种存储器系统，其中存储器模块之间的数据传输时间被管理，使得存储器系统中的指定点之间的总体时间延迟保持恒定。 可以单独管理多车道总线的每条通道，并且在目的地模块处评估数据帧，而不需要在中间模块处进行纠偏。 通过在总线串行数据速率的一个或多个约数处操作通过模块的数据路径，并选择数据路径的采样点来减少通过可能具有切换数据路由的模块的数据传播的时间延迟 接收到的数据，以适应由于温度变化或老化引起的时间延迟的变化。

公开(公告)号：WO2011079298A3

公开(公告)日：2011-11-17

申请号：PCT/US2010062061

申请日：2010-12-23

Applicant: VIOLIN MEMORY INC ,  BENNETT JON C R

Inventor： BENNETT JON C R

IPC: G06F13/14

CPC classification number: G06F13/1684 ,  G06F13/14 ,  G06F13/36 ,  G11C19/00 ,  H03K19/17 ,  Y02D10/14

Abstract: An interconnection system, apparatus and method is described where the motherboard may be populated with less than all of the modules that it has been designed to accept while maintaining a configuration such that in the event of a module failure, a memory controller failure, or a combination thereof, the connectivity of the remaining modules is maintained. Where data is stored using a RAID organization of the memory on the modules, the data may be reconstructed to a spare module. The system also provides for the orderly incremental expansion of the memory by adding additional memory modules and memory controllers, while maintaining the connectivity properties.

Abstract translation: 描述了一种互连系统，装置和方法，其中母板可以被填充少于其被设计为接受的所有模块，同时保持配置，使得在模块故障，存储器控制器故障或 其组合，保持其余模块的连接性。 在使用模块上的存储器的RAID组织存储数据的情况下，可以将数据重建为备用模块。 该系统还通过添加额外的内存模块和内存控制器，同时保持连接性能，从而有序地增加内存的扩展。

公开(公告)号：WO2009032751A3

公开(公告)日：2009-05-07

申请号：PCT/US2008074628

申请日：2008-08-28

Applicant: VIOLIN MEMORY INC ,  ADELMAN MAXIM ,  BENNETT JON C R

Inventor： ADELMAN MAXIM ,  BENNETT JON C R

IPC: G06F12/00

CPC classification number: G11C11/4076 ,  G06F1/3203 ,  G06F1/3225 ,  G06F1/3275 ,  G06F3/0608 ,  G06F3/064 ,  G06F3/0652 ,  G06F3/0688 ,  G06F3/0689 ,  G11C5/04 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/4074 ,  G11C2211/4067 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D50/20

Abstract: A memory system is described, where a plurality of memory modules is connected to a memory controller. The power status of each of the memory modules is controlled, depending on the functions being performed by the memory module. When no read or write operation is being performed on a particular memory module, at least a portion of the circuitry may be operated in a lower power mode. A memory circuit associated with the memory module may be placed in a low power mode by disabling a clock. The memory circuit data integrity may be secured by issuing refresh commands while when the memory circuit is in the lower power mode, by enabling the clock, issuing the refresh command, and disabling the clock after completion of the refresh operation.

Abstract translation: 描述了一种存储器系统，其中多个存储器模块连接到存储器控制器。 根据内存模块执行的功能，每个内存模块的电源状态都受到控制。 当没有对特定存储器模块执行读取或写入操作时，电路的至少一部分可以以较低功率模式操作。 与存储器模块相关联的存储器电路可以通过禁用时钟而置于低功率模式。 当存储器电路处于较低功率模式时，通过发出刷新命令，通过启用时钟，发出刷新命令，并且在完成刷新操作之后禁用时钟，可以保证存储器电路数据完整性。

公开(公告)号：WO2011044515A2

公开(公告)日：2011-04-14

申请号：PCT/US2010052074

申请日：2010-10-08

Applicant: VIOLIN MEMORY INC ,  BENNETT JON C R

Inventor： BENNETT JON C R

IPC: G06F12/16 ,  G06F13/14

CPC classification number: G06F11/1092 ,  G06F2211/1061

Abstract: A data memory system is described, where there may be an asymmetry in the time needed to write or erase data and the time needed to read data. The data may be stored using a RAID data storage arrangement and the reading, writing and erasing operations on the modules arranged such that the erasing and writing operations may be performed without significant latency for performing a read operation. Where a failure of a memory module in the memory system occurs, methods for recovering the data of the failed module are disclosed which may selected in accordance with policies that may relate to the minimizing the possibility of irretrievable data loss, or degradation of latency performance.

Abstract translation: 描述了一种数据存储系统，其中写入或擦除数据所需的时间可能不对称，以及读取数据所需的时间。 可以使用RAID数据存储装置存储数据，并且对布置的模块进行读取，写入和擦除操作，使得可以执行擦除和写入操作而没有用于执行读取操作的显着延迟。 在存储器系统中的存储器模块发生故障的情况下，公开了用于恢复故障模块的数据的方法，其可以根据可能涉及最小化不可恢复的数据丢失的可能性或延迟性能下降的策略来选择。

公开(公告)号：WO2008121306A9

公开(公告)日：2009-04-09

申请号：PCT/US2008004015

申请日：2008-03-27

Applicant: VIOLIN MEMORY INC ,  BENNETT JON C R

Inventor： BENNETT JON C R

IPC: G06F12/08 ,  G11B20/18

CPC classification number: G06F3/065 ,  G06F3/0608 ,  G06F3/0616 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0652 ,  G06F3/0653 ,  G06F3/0688 ,  G06F3/0689 ,  G06F11/1044 ,  G06F11/1068 ,  G06F11/1072 ,  G06F11/1076 ,  G06F11/108 ,  G06F12/0246 ,  G06F12/0866 ,  G11B20/1833 ,  G11B2220/60 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C29/28 ,  G11C29/52

公开(公告)号：WO2013009994A3

公开(公告)日：2013-04-25

申请号：PCT/US2012046487

申请日：2012-07-12

Applicant: VIOLIN MEMORY INC ,  BENNETT JON C R ,  SMITH DAVID M ,  BIEDERMAN DANIEL C

Inventor： BENNETT JON C R ,  SMITH DAVID M ,  BIEDERMAN DANIEL C

IPC: G06F13/14 ,  G06F13/16

CPC classification number: G06F3/0688 ,  G06F3/0611 ,  G06F3/0614 ,  G06F3/0659 ,  G06F3/0689

Abstract: A memory system and a method for managing the system is described. The system is configured such a plurality of system controllers, which may be RAID controllers, receive requests from the external environment and distribute the requests to a plurality of memory modules such that data may be stored in the memory modules. A global sequence number is assigned to the data of a data stripe so that the operations related to the data stripe are performed in an ordered manner so that the data remains consistent. A plurality of system controllers may comprise a domain and access a plurality of memory controllers and a plurality of domains may include at least one common memory module.

Abstract translation: 描述了一种用于管理该系统的存储器系统和方法。 该系统被配置为使得多个系统控制器（其可以是RAID控制器）接收来自外部环境的请求并将请求分配给多个存储器模块，使得数据可以被存储在存储器模块中。 将全局序列号分配给数据条带的数据，以便与数据条带相关的操作以有序的方式执行，以使数据保持一致。 多个系统控制器可以包括域并访问多个存储器控制器，并且多个域可以包括至少一个公共存储器模块。

公开(公告)号：WO2010144587A2

公开(公告)日：2010-12-16

申请号：PCT/US2010037987

申请日：2010-06-09

Applicant: VIOLIN MEMORY INC ,  BENNETT JON C R

Inventor： BENNETT JON C R

IPC: G06F12/02 ,  G06F12/06

CPC classification number: G06F12/0246 ,  G06F2212/7205

Abstract: Non-volatile memory systems such as those using NAND FLASH technology have a property that a memory location can be written to only once prior to being erased, and a contiguous group of memory locations need to be erased simultaneously. The process of recovering space that is no longer being used for storage of current data, called garbage collection, may interfere with the rapid access to data in other memory locations of the memory system during the erase period. The effects of garbage collection on system performance may be mitigated by performing portions of the process contemporaneously with the user initiated reading and writing operations. The memory circuits and the data may also be configured such that the data is stored in stripes of a RAID array and the scheduling of the erase operations may be arranged so that the erase operations for garbage collection are hidden from the user operations.

Abstract translation: 非易失性存储器系统，例如使用NAND FLASH技术的存储器系统具有的性质在于，可以在擦除之前将存储器位置写入仅一次，并且需要同时擦除连续的一组存储器位置。 恢复不再用于存储当前数据（称为垃圾回收）的空间的过程可能会在擦除周期期间干扰对存储器系统的其他存储单元中的数据的快速访问。 垃圾收集对系统性能的影响可以通过与用户启动的读写操作同时执行该过程的一部分来减轻。 存储器电路和数据也可以被配置为使得数据以RAID阵列的条带存储，并且可以布置擦除操作的调度，使得垃圾收集的擦除操作从用户操作中隐藏。

公开(公告)号：WO2009067476A3

公开(公告)日：2009-07-09

申请号：PCT/US2008083969

申请日：2008-11-19

Applicant: VIOLIN MEMORY INC ,  BENNETT JON C R

Inventor： BENNETT JON C R

IPC: G06F12/00 ,  G06F9/06 ,  G06F12/06 ,  G06F13/00

CPC classification number: G06F12/0246 ,  G06F11/1441 ,  G06F11/1471 ,  G06F11/1474 ,  G06F2212/1008 ,  G06F2212/7205 ,  G06F2212/7207 ,  G06F2212/7209

Abstract: A system and method for managing the storage of data in non-volatile memory is described. In an aspect, the data may be described by metadata and a transaction log file that are checkpointed from a volatile memory into the non-volatile memory. Actions that take place between the last checkpointing of a metadata segment and log file segment are discovered by scanning the non-volatile memory blocks, taking account of a record of the highest sector in each block that is known to have been recorded. Any later transactions are discovered and used to update the recovered metadata so that the metadata correctly represents the stored data.

Abstract translation: 描述了用于管理非易失性存储器中的数据存储的系统和方法。 在一个方面中，数据可以通过元数据和事务日志文件来描述，所述元数据和事务日志文件从易失性存储器检查点到非易失性存储器中。 通过扫描非易失性存储器块来发现在元数据段和日志文件段的最后一次检查点之间发生的动作，同时考虑到已知已经记录的每个块中最高扇区的记录。 任何后来的事务都会被发现并用于更新已恢复的元数据，以便元数据正确表示已存储的数据。

公开(公告)号：WO2006115896A3

公开(公告)日：2007-05-31

申请号：PCT/US2006014527

申请日：2006-04-17

Applicant: VIOLIN TECHNOLOGIES ,  BENNETT JON C R

Inventor： BENNETT JON C R

IPC: G06F1/26

CPC classification number: G06F13/4027 ,  G06F13/1684 ,  G06F13/4243 ,  G06F13/4247 ,  Y02D10/14 ,  Y02D10/151

Abstract: An interconnection system, apparatus and method is described for arranging elements in a network, which may be a data memory system, computing system or communications system where the data paths are arranged and operated so as to control the power consumption and data skew properties of the system. A configurable switching element may be used to form the interconnections at nodes, where a control signal and other information is used to manage the power status of other aspects of the configurable switching element. Time delay skew of data being transmitted between nodes of the network may be altered by exchanging the logical and physical line assignments of the data at one or more nodes of the network. A method of laying out an interconnecting motherboard is disclosed which reduces the complexity of the trace routing.

Abstract translation: 描述了用于在网络中布置元件的互连系统，装置和方法，网络中的元件可以是数据存储器系统，计算系统或通信系统，其中数据路径被布置和操作，以便控制数据路径的功耗和数据歪斜特性 系统。 可以使用可配置的开关元件在节点处形成互连，其中使用控制信号和其他信息来管理可配置开关元件的其他方面的电力状态。 可以通过在网络的一个或多个节点处交换数据的逻辑和物理线路分配来改变在网络节点之间传输的数据的时间延迟偏差。 公开了布置互连主板的方法，其降低了跟踪路由的复杂性。