Abstract:
Systems and methods for generating and using a placement map for a distributed storage system are disclosed. In some embodiments, a method for a client node to perform a read/write operation in a distributed storage system comprises obtaining a number of server nodes comprised in the distributed storage system and an object name of an object for which a read/write operation is to be performed and creating at least a portion of a three-dimensional (3D) placement map for the object. The 3D placement map defines candidate locations for replicas of the object on the server nodes. The method further comprises applying policies to the at least a portion of the 3D placement map to provide at least a portion of a modified 3D placement map and performing the read/write operation for the object in accordance with the at least a portion of the modified 3D placement map.
Abstract:
Systems, devices, and methods for managing fragmentation in hardware-assisted compression of data in physical computer memory which may result in reduced internal fragmentation. An example computer-implemented method comprises: providing, by a memory management program to compression hardware, a compression command including an address in physical computer memory of data to be compressed and a list of at least two available buffers for storing compressed data; using, by the compression hardware, the address included in the compression command to retrieve uncompressed data; compressing the uncompressed data; and selecting, by the compression hardware, from the list of at least two available buffers, at least two buffers for storing compressed data based on an amount of space that would remain if the compressed data were stored in the at least two buffers, wherein each of the at least two selected buffers differs in size from at least one other of the selected buffers.
Abstract:
A system for enforcing restrictive access control with respect to a set of digital objects includes a first device. The first device is configured to: determine, based at least in part on a first access control rule, to block access to at least a first digital object included in the set of digital objects; determine, based at least in part on a second access control rule, to block access to at least a second digital object included in the set of digital objects; and provide, to a user of the first device, at least a third digital object included in the set of digital objects but not the first digital object and the second digital object.
Abstract:
Example implementations relate to a storage memory direct access (SMDA) provider. The SMDA provider may pin a storage memory region to a memory address of a consumer machine, the storage memory region corresponding to a storage range of a storage device requested by the consumer machine. The SMDA provider may atomically commit data in the storage memory region accessed by the consumer machine via the memory address.
Abstract:
In embodiments of battery-backed RAM for wearable devices, a mobile device, such as a mobile phone, tablet computer, or other portable device is implemented for wireless connection with a wearable device, such as a smartwatch, exercise tracking device, glasses device, or other wearable device that implements computing technology. The wearable device can store data in battery-backed RAM in the wearable device, and the mobile device can back-up the data with battery-backed RAM in the mobile device when the data is received from the wearable device. A wireless connection can be established for wireless data communication between the wearable device and the mobile device. A data manager can detect a low battery condition of the wearable device, which initiates the data being transferred from the wearable device to the mobile device via the wireless connection.
Abstract:
Embodiments of the invention provide systems and methods to implement an object memory fabric including hardware-based processing nodes having memory modules storing and managing memory objects created natively within the memory modules and managed by the memory modules at a memory layer, where physical address of memory and storage is managed with the memory objects based on an object address space that is allocated on a per-object basis with an object addressing scheme. Each node may utilize the object addressing scheme to couple to additional nodes to operate as a set of nodes so that all memory objects of the set are accessible based on the object addressing scheme defining invariant object addresses for the memory objects that are invariant with respect to physical memory storage locations and storage location changes of the memory objects within the memory module and across all modules interfacing the object memory fabric.
Abstract:
Provided are methods and systems for de-duplicating cache lines in physical memory by detecting cache line data patterns and building a link-list between multiple physical addresses and their common data value. In this manner, the methods and systems are applied to achieve de-duplication of an on-chip cache. A cache line filter includes one table that defines the most commonly duplicated content patterns and a second table that saves pattern numbers from the first table and the physical address for the duplicated cache line. Since a cache line duplicate can be detected during a write operation, each write can involve table lookup and comparison. If there is a hit in the table, only the address is saved instead of the entire data string.
Abstract:
Provided are methods and systems for managing memory using a hardware-based page filter designed to distinguish between active and inactive pages ("hot" and "cold" pages, respectively) so that inactive pages can be compressed prior to the occurrence of a page fault. The methods and systems are designed to achieve, among other things, lower cost, longer battery life, and faster user response. Whereas existing approaches for memory management are based on pixel or frame buffer compression, the methods and systems provided focus on the CPU's program (e.g., generic data structure). Focusing on hardware-accelerated memory compression to offload CPU translates higher power efficiency (e.g., ASIC is approximately 100x lower power than CPU) and higher performance (e.g., ASIC is approximately 10x faster than CPU), and also allows for hardware-assisted memory management to offload OS/kernel, which significantly increases response time.