公开(公告)号：WO2018063403A1

公开(公告)日：2018-04-05

申请号：PCT/US2016/055028

申请日：2016-09-30

Applicant: INTEL CORPORATION

Inventor： DEWEY, Gilbert ,  METZ, Matthew V. ,  MA, Sean T. ,  HUANG, Cheng-Ying ,  GHANI, Tahir ,  MURTHY, Anand S. ,  KENNEL, Harold W. ,  MINUTILLO, Nicholas G. ,  KAVALIEROS, Jack T. ,  RACHMADY, Willy

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L21/8234

Abstract: A transistor device comprising a channel disposed on a substrate between a source and a drain, a gate electrode disposed on the channel, wherein the channel comprises a channel material that is separated from a body of the same material on a substrate. A method comprising forming a trench in a dielectric layer on an integrated circuit substrate, the trench comprising dimensions for a transistor body including a width; depositing a spacer layer in a portion of the trench, the spacer layer narrowing the width of the trench; forming a channel material in the trench through the spacer layer; recessing the dielectric layer to define a first portion of the channel material exposed and a second portion of the channel material in the trench; and separating the first portion of the channel material from the second portion of the channel material.

Abstract translation: 一种晶体管器件，包括设置在源极和漏极之间的衬底上的沟道，设置在所述沟道上的栅电极，其中所述沟道包括沟道材料，所述沟道材料与相同材料的本体分离 在衬底上。 一种方法，包括在集成电路衬底上的电介质层中形成沟槽，所述沟槽包括用于包括宽度的晶体管主体的尺寸; 在沟槽的一部分中沉积间隔层，间隔层使沟槽的宽度变窄; 穿过间隔层在沟槽中形成沟道材料; 使所述介电层凹陷以限定所述沟道材料的第一部分和所述沟道材料的第二部分; 以及将沟道材料的第一部分与沟道材料的第二部分分开。

公开(公告)号：WO2018063372A1

公开(公告)日：2018-04-05

申请号：PCT/US2016/054911

申请日：2016-09-30

Applicant: INTEL CORPORATION

Inventor： HUANG, Cheng-Ying ,  METZ, Matthew V. ,  RACHMADY, Willy ,  DEWEY, Gilbert ,  KAVALIEROS, Jack T.

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/423

Abstract: An embodiment includes an apparatus comprising: a trench included in an insulation layer that is formed on a substrate, the trench having a top portion and a bottom portion between the top portion and the substrate; a first layer which comprises a first material and is included in the bottom portion; and a superlattice, in the trench and on the first layer, including second and third layers that directly contact each other; wherein: (a) the second and third layers respectively include second and third materials, (b) the second and third materials have different chemical compositions from each other, and (c) the first layer is thicker than each of the second and third. Other embodiments are described herein.

Abstract translation: 一种实施方式包括一种装置，该装置包括：包括在形成在基板上的绝缘层中的沟槽，所述沟槽具有位于所述顶部和所述基板之间的顶部和底部; 包含第一材料并包含在底部中的第一层; 和超晶格，在沟槽中和第一层上，包括彼此直接接触的第二层和第三层; 其中：（a）第二和第三层分别包括第二和第三材料，（b）第二和第三材料彼此具有不同的化学组成，并且（c）第一层比第二和第三层中的每一个都厚。 这里描述了其他实施例。

公开(公告)号：WO2018063290A1

公开(公告)日：2018-04-05

申请号：PCT/US2016/054676

申请日：2016-09-30

Applicant: INTEL CORPORATION

Inventor： METZ, Matthew ,  DEWEY, Gilbert ,  KENNEL, Harold W. ,  HUANG, Cheng-Ying ,  MA, Sean T. ,  RACHMADY, Willy

IPC: H01L29/12 ,  H01L21/02 ,  H01L21/20

CPC classification number: H01L29/122 ,  H01L21/02543 ,  H01L21/02546 ,  H01L29/20

Abstract: Semiconductor devices, computing devices, and related methods are disclosed herein. A semiconductor device includes a seed material, an epitaxial material in contact with the seed material, and at least one quantum region including an elastic stiffness that is greater than an elastic stiffness of the epitaxial material. The epitaxial material has lattice parameters that are different from lattice parameters of the seed material by at least a threshold amount. Lattice parameters of the quantum region are within the threshold amount of the lattice parameters of the epitaxial material. A method includes disposing an epitaxial material on a seed material, disposing a quantum region on the epitaxial material, and disposing the epitaxial material on the quantum region.

Abstract translation: 这里公开了半导体器件，计算设备和相关方法。 一种半导体器件包括种子材料，与种子材料接触的外延材料以及包括大于外延材料的弹性刚度的弹性刚度的至少一个量子区域。 外延材料具有与晶种材料的晶格参数相差至少阈值量的晶格参数。 量子区域的晶格参数在外延材料的晶格参数的阈值量内。 一种方法包括在种子材料上设置外延材料，在外延材料上设置量子区域，并在该量子区域上设置外延材料。

公开(公告)号：WO2018057043A1

公开(公告)日：2018-03-29

申请号：PCT/US2016/053831

申请日：2016-09-26

Applicant: INTEL CORPORATION

Inventor： HUANG, Cheng-Ying ,  RACHMADY, Willy ,  METZ, Matthew V. ,  DEWEY, Gilbert ,  KAVALIEROS, Jack T. ,  MA, Sean T. ,  KENNEL, Harold

IPC: H01L29/78 ,  H01L29/778 ,  H01L29/06 ,  H01L21/768

Abstract: A buffer layer is deposited on a substrate. A first III-V semiconductor layer is deposited on the buffer layer. A second III-V semiconductor layer is deposited on the first III-V semiconductor layer. The second III-V semiconductor layer comprises a channel portion and a source/drain portion. The first III-V semiconductor layer acts as an etch stop layer to etch a portion of the second III-V semiconductor layer to form the source/drain portion.

Abstract translation: 缓冲层沉积在衬底上。 第一III-V族半导体层沉积在缓冲层上。 在第一III-V半导体层上沉积第二III-V族半导体层。 第二III-V族半导体层包括沟道部分和源极/漏极部分。 第一III-V半导体层用作蚀刻停止层以蚀刻第二III-V族半导体层的一部分以形成源极/漏极部分。